synctime.vhd

利用Ti公司的TMSvc320c6711开发板的基础上搭建的移动视频电话系统。程序中主要实现3个功能：实时捕捉视频和音频数据；能够对视频和音频数据进行解码和存储；能够通过GPRS通信口传输音/视频压缩

-- Author: Elliot Hill
--
-- Description: This file is the module for the synchronisation of events
-- such as triggering DMA transfers, and when to store the
-- Y and UV data from the TVP5040.
--
-- Last Modified: 2 October 2001
--
library ieee;
use ieee.std_logic_1164.all;
entity synctime is
port (high,clk,hsyncro,vblank,irq7fb,vsyncro,FIDin,xcntrl: in BIT;
primclk,secclk,t1pin,irq7: out BIT);
end;
architecture synctime of synctime is
-- The D Flip Flop Component
component DFLIPFLOP
port (D,clk,reset: in BIT;
Q: out BIT);
end component;
-- The T Flip Flop Component
component TFF
port (T, clk, reset: in BIT;
Q: out BIT);
end component;
-- The Counter component
component counter
port (clkin, reset: in BIT;
total: in INTEGER;
OE: out BIT);
end component;
signal outLSync : BIT := '0';
signal eoactive : BIT := '0';
signal blankinv : BIT;
signal vblatchout : BIT := '0';
signal pixelready : BIT := '0';
signal fifthline : BIT := '0';
begin
blankinv <= not vblank;
-- Three counters used within the synctime module. The first
-- counter is used for counting the number of active pixels
-- per line. The second and third counters are used for
-- counting to the 5th line and pixel (respectively).
C1: counter port map (clk,hsyncro,720,eoactive);
C2: counter port map (hsyncro,'0',5,fifthline);
C3: counter port map (pixelready,'0',5,t1pin);
-- This T flip flop is used for the generation of the register
-- clocking signals. The two D flipflops are used as latches
-- to hold the signals informing other components of
-- active signal regions and vertical blanking intervals.
T1: TFF port map (high,clk,vsyncro,primclk);
D1: DFLIPFLOP port map (high,hsyncro,eoactive,outLSync);
D2: DFLIPFLOP port map (high,blankinv,irq7fb,vblatchout);
-- Pixelready determines when a valid pixel is ready to be read
-- by the DMA controller, and this is used as an input to the
-- 5th pixel counter. irq7 signal triggers the EXT_IRQ7 line, and
-- secclk is used to clock the register module.
pixelready <= clk and outLSync and vblatchout and fifthline;
irq7 <= xcntrl and (vsyncro and FIDin);
secclk <= not primclk;
end synctime;