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<h4 class="subsection">DEC Alpha Options</h4>



   <p>These <code>-m</code> options are defined for the DEC Alpha implementations:



     <dl>

<dt><code>-mno-soft-float</code>

     <dd><dt><code>-msoft-float</code>

     <dd>Use (do not use) the hardware floating-point instructions for

floating-point operations.  When <code>-msoft-float</code> is specified,

functions in <code>libgcc.a</code> will be used to perform floating-point

operations.  Unless they are replaced by routines that emulate the

floating-point operations, or compiled in such a way as to call such

emulations routines, these routines will issue floating-point

operations.   If you are compiling for an Alpha without floating-point

operations, you must ensure that the library is built so as not to call

them.



     <p>Note that Alpha implementations without floating-point operations are

required to have floating-point registers.



     <br><dt><code>-mfp-reg</code>

     <dd><dt><code>-mno-fp-regs</code>

     <dd>Generate code that uses (does not use) the floating-point register set. 

<code>-mno-fp-regs</code> implies <code>-msoft-float</code>.  If the floating-point

register set is not used, floating point operands are passed in integer

registers as if they were integers and floating-point results are passed

in <code>$0</code> instead of <code>$f0</code>.  This is a non-standard calling sequence,

so any function with a floating-point argument or return value called by code

compiled with <code>-mno-fp-regs</code> must also be compiled with that

option.



     <p>A typical use of this option is building a kernel that does not use,

and hence need not save and restore, any floating-point registers.



     <br><dt><code>-mieee</code>

     <dd>The Alpha architecture implements floating-point hardware optimized for

maximum performance.  It is mostly compliant with the IEEE floating

point standard.  However, for full compliance, software assistance is

required.  This option generates code fully IEEE compliant code

<em>except</em> that the <var>inexact-flag</var> is not maintained (see below). 

If this option is turned on, the preprocessor macro <code>_IEEE_FP</code> is

defined during compilation.  The resulting code is less efficient but is

able to correctly support denormalized numbers and exceptional IEEE

values such as not-a-number and plus/minus infinity.  Other Alpha

compilers call this option <code>-ieee_with_no_inexact</code>.



     <br><dt><code>-mieee-with-inexact</code>

     <dd>This is like <code>-mieee</code> except the generated code also maintains

the IEEE <var>inexact-flag</var>.  Turning on this option causes the

generated code to implement fully-compliant IEEE math.  In addition to

<code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessor

macro.  On some Alpha implementations the resulting code may execute

significantly slower than the code generated by default.  Since there is

very little code that depends on the <var>inexact-flag</var>, you should

normally not specify this option.  Other Alpha compilers call this

option <code>-ieee_with_inexact</code>.



     <br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><code></code>

     <dd>This option controls what floating-point related traps are enabled. 

Other Alpha compilers call this option <code>-fptm </code><var>trap-mode</var><code></code>. 

The trap mode can be set to one of four values:



          <dl>

<dt><code>n</code>

          <dd>This is the default (normal) setting.  The only traps that are enabled

are the ones that cannot be disabled in software (e.g., division by zero

trap).



          <br><dt><code>u</code>

          <dd>In addition to the traps enabled by <code>n</code>, underflow traps are enabled

as well.



          <br><dt><code>su</code>

          <dd>Like <code>su</code>, but the instructions are marked to be safe for software

completion (see Alpha architecture manual for details).



          <br><dt><code>sui</code>

          <dd>Like <code>su</code>, but inexact traps are enabled as well. 

</dl>



     <br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><code></code>

     <dd>Selects the IEEE rounding mode.  Other Alpha compilers call this option

<code>-fprm </code><var>rounding-mode</var><code></code>.  The <var>rounding-mode</var> can be one

of:



          <dl>

<dt><code>n</code>

          <dd>Normal IEEE rounding mode.  Floating point numbers are rounded towards

the nearest machine number or towards the even machine number in case

of a tie.



          <br><dt><code>m</code>

          <dd>Round towards minus infinity.



          <br><dt><code>c</code>

          <dd>Chopped rounding mode.  Floating point numbers are rounded towards zero.



          <br><dt><code>d</code>

          <dd>Dynamic rounding mode.  A field in the floating point control register

(<var>fpcr</var>, see Alpha architecture reference manual) controls the

rounding mode in effect.  The C library initializes this register for

rounding towards plus infinity.  Thus, unless your program modifies the

<var>fpcr</var>, <code>d</code> corresponds to round towards plus infinity. 

</dl>



     <br><dt><code>-mtrap-precision=</code><var>trap-precision</var><code></code>

     <dd>In the Alpha architecture, floating point traps are imprecise.  This

means without software assistance it is impossible to recover from a

floating trap and program execution normally needs to be terminated. 

GCC can generate code that can assist operating system trap handlers

in determining the exact location that caused a floating point trap. 

Depending on the requirements of an application, different levels of

precisions can be selected:



          <dl>

<dt><code>p</code>

          <dd>Program precision.  This option is the default and means a trap handler

can only identify which program caused a floating point exception.



          <br><dt><code>f</code>

          <dd>Function precision.  The trap handler can determine the function that

caused a floating point exception.



          <br><dt><code>i</code>

          <dd>Instruction precision.  The trap handler can determine the exact

instruction that caused a floating point exception. 

</dl>



     <p>Other Alpha compilers provide the equivalent options called

<code>-scope_safe</code> and <code>-resumption_safe</code>.



     <br><dt><code>-mieee-conformant</code>

     <dd>This option marks the generated code as IEEE conformant.  You must not

use this option unless you also specify <code>-mtrap-precision=i</code> and either

<code>-mfp-trap-mode=su</code> or <code>-mfp-trap-mode=sui</code>.  Its only effect

is to emit the line <code>.eflag 48</code> in the function prologue of the

generated assembly file.  Under DEC Unix, this has the effect that

IEEE-conformant math library routines will be linked in.



     <br><dt><code>-mbuild-constants</code>

     <dd>Normally GCC examines a 32- or 64-bit integer constant to

see if it can construct it from smaller constants in two or three

instructions.  If it cannot, it will output the constant as a literal and

generate code to load it from the data segment at runtime.



     <p>Use this option to require GCC to construct <em>all</em> integer constants

using code, even if it takes more instructions (the maximum is six).



     <p>You would typically use this option to build a shared library dynamic

loader.  Itself a shared library, it must relocate itself in memory

before it can find the variables and constants in its own data segment.



     <br><dt><code>-malpha-as</code>

     <dd><dt><code>-mgas</code>

     <dd>Select whether to generate code to be assembled by the vendor-supplied

assembler (<code>-malpha-as</code>) or by the GNU assembler <code>-mgas</code>.



     <br><dt><code>-mbwx</code>

     <dd><dt><code>-mno-bwx</code>

     <dd><dt><code>-mcix</code>

     <dd><dt><code>-mno-cix</code>

     <dd><dt><code>-mfix</code>

     <dd><dt><code>-mno-fix</code>

     <dd><dt><code>-mmax</code>

     <dd><dt><code>-mno-max</code>

     <dd>Indicate whether GCC should generate code to use the optional BWX,

CIX, FIX and MAX instruction sets.  The default is to use the instruction

sets supported by the CPU type specified via <code>-mcpu=</code> option or that

of the CPU on which GCC was built if none was specified.



     <br><dt><code>-mfloat-vax</code>

     <dd><dt><code>-mfloat-ieee</code>

     <dd>Generate code that uses (does not use) VAX F and G floating point

arithmetic instead of IEEE single and double precision.



     <br><dt><code>-mexplicit-relocs</code>

     <dd><dt><code>-mno-explicit-relocs</code>

     <dd>Older Alpha assemblers provided no way to generate symbol relocations

except via assembler macros.  Use of these macros does not allow

optimal instruction scheduling.  GNU binutils as of version 2.12

supports a new syntax that allows the compiler to explicitly mark

which relocations should apply to which instructions.  This option

is mostly useful for debugging, as GCC detects the capabilities of

the assembler when it is built and sets the default accordingly.



     <br><dt><code>-msmall-data</code>

     <dd><dt><code>-mlarge-data</code>

     <dd>When <code>-mexplicit-relocs</code> is in effect, static data is

accessed via <dfn>gp-relative</dfn> relocations.  When <code>-msmall-data</code>

is used, objects 8 bytes long or smaller are placed in a <dfn>small data area</dfn>

(the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via

16-bit relocations off of the <code>$gp</code> register.  This limits the

size of the small data area to 64KB, but allows the variables to be

directly accessed via a single instruction.



     <p>The default is <code>-mlarge-data</code>.  With this option the data area

is limited to just below 2GB.  Programs that require more than 2GB of

data must use <code>malloc</code> or <code>mmap</code> to allocate the data in the

heap instead of in the program's data segment.



     <p>When generating code for shared libraries, <code>-fpic</code> implies

<code>-msmall-data</code> and <code>-fPIC</code> implies <code>-mlarge-data</code>.



     <br><dt><code>-mcpu=</code><var>cpu_type</var><code></code>

     <dd>Set the instruction set and instruction scheduling parameters for

machine type <var>cpu_type</var>.  You can specify either the <code>EV</code>

style name or the corresponding chip number.  GCC supports scheduling

parameters for the EV4, EV5 and EV6 family of processors and will

choose the default values for the instruction set from the processor

you specify.  If you do not specify a processor type, GCC will default

to the processor on which the compiler was built.



     <p>Supported values for <var>cpu_type</var> are



          <dl>

<dt><code>ev4</code>

          <dd><br><dt><code>ev45</code>

          <dd><dt><code>21064</code>

          <dd>Schedules as an EV4 and has no instruction set extensions.



          <br><dt><code>ev5</code>

          <dd><dt><code>21164</code>

          <dd>Schedules as an EV5 and has no instruction set extensions.



          <br><dt><code>ev56</code>

          <dd><dt><code>21164a</code>

          <dd>Schedules as an EV5 and supports the BWX extension.



          <br><dt><code>pca56</code>

          <dd><dt><code>21164pc</code>

          <dd><dt><code>21164PC</code>

          <dd>Schedules as an EV5 and supports the BWX and MAX extensions.



          <br><dt><code>ev6</code>

          <dd><dt><code>21264</code>

          <dd>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.



          <br><dt><code>ev67</code>

          <dd><br><dt><code>21264a</code>

          <dd>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions. 

</dl>



     <br><dt><code>-mtune=</code><var>cpu_type</var><code></code>

     <dd>Set only the instruction scheduling parameters for machine type

<var>cpu_type</var>.  The instruction set is not changed.



     <br><dt><code>-mmemory-latency=</code><var>time</var><code></code>

     <dd>Sets the latency the scheduler should assume for typical memory

references as seen by the application.  This number is highly

dependent on the memory access patterns used by the application

and the size of the external cache on the machine.



     <p>Valid options for <var>time</var> are



          <dl>

<dt><code></code><var>number</var><code></code>

          <dd>A decimal number representing clock cycles.



          <br><dt><code>L1</code>

          <dd><dt><code>L2</code>

          <dd><dt><code>L3</code>

          <dd><dt><code>main</code>

          <dd>The compiler contains estimates of the number of clock cycles for

"typical" EV4 &amp; EV5 hardware for the Level 1, 2 &amp; 3 caches

(also called Dcache, Scache, and Bcache), as well as to main memory. 

Note that L3 is only valid for EV5.



     </dl>

</dl>



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