machine-constraints.html

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     <br><dt><em>Intel 960--</em><code>i960.h</code><em></em>
     <dd>
          <dl>
<dt><code>f</code>
          <dd>Floating point register (<code>fp0</code> to <code>fp3</code>)

          <br><dt><code>l</code>
          <dd>Local register (<code>r0</code> to <code>r15</code>)

          <br><dt><code>b</code>
          <dd>Global register (<code>g0</code> to <code>g15</code>)

          <br><dt><code>d</code>
          <dd>Any local or global register

          <br><dt><code>I</code>
          <dd>Integers from 0 to 31

          <br><dt><code>J</code>
          <dd>0

          <br><dt><code>K</code>
          <dd>Integers from -31 to 0

          <br><dt><code>G</code>
          <dd>Floating point 0

          <br><dt><code>H</code>
          <dd>Floating point 1
</dl>

     <br><dt><em>Intel IA-64--</em><code>ia64.h</code><em></em>
     <dd>
          <dl>
<dt><code>a</code>
          <dd>General register <code>r0</code> to <code>r3</code> for <code>addl</code> instruction

          <br><dt><code>b</code>
          <dd>Branch register

          <br><dt><code>c</code>
          <dd>Predicate register (<code>c</code> as in "conditional")

          <br><dt><code>d</code>
          <dd>Application register residing in M-unit

          <br><dt><code>e</code>
          <dd>Application register residing in I-unit

          <br><dt><code>f</code>
          <dd>Floating-point register

          <br><dt><code>m</code>
          <dd>Memory operand. 
Remember that <code>m</code> allows postincrement and postdecrement which
require printing with <code>%Pn</code> on IA-64. 
Use <code>S</code> to disallow postincrement and postdecrement.

          <br><dt><code>G</code>
          <dd>Floating-point constant 0.0 or 1.0

          <br><dt><code>I</code>
          <dd>14-bit signed integer constant

          <br><dt><code>J</code>
          <dd>22-bit signed integer constant

          <br><dt><code>K</code>
          <dd>8-bit signed integer constant for logical instructions

          <br><dt><code>L</code>
          <dd>8-bit adjusted signed integer constant for compare pseudo-ops

          <br><dt><code>M</code>
          <dd>6-bit unsigned integer constant for shift counts

          <br><dt><code>N</code>
          <dd>9-bit signed integer constant for load and store postincrements

          <br><dt><code>O</code>
          <dd>The constant zero

          <br><dt><code>P</code>
          <dd>0 or -1 for <code>dep</code> instruction

          <br><dt><code>Q</code>
          <dd>Non-volatile memory for floating-point loads and stores

          <br><dt><code>R</code>
          <dd>Integer constant in the range 1 to 4 for <code>shladd</code> instruction

          <br><dt><code>S</code>
          <dd>Memory operand except postincrement and postdecrement
</dl>

     <br><dt><em>FRV--</em><code>frv.h</code><em></em>
     <dd>
          <dl>
<dt><code>a</code>
          <dd>Register in the class <code>ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

          <br><dt><code>b</code>
          <dd>Register in the class <code>EVEN_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

          <br><dt><code>c</code>
          <dd>Register in the class <code>CC_REGS</code> (<code>fcc0</code> to <code>fcc3</code> and
<code>icc0</code> to <code>icc3</code>).

          <br><dt><code>d</code>
          <dd>Register in the class <code>GPR_REGS</code> (<code>gr0</code> to <code>gr63</code>).

          <br><dt><code>e</code>
          <dd>Register in the class <code>EVEN_REGS</code> (<code>gr0</code> to <code>gr63</code>). 
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.

          <br><dt><code>f</code>
          <dd>Register in the class <code>FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>).

          <br><dt><code>h</code>
          <dd>Register in the class <code>FEVEN_REGS</code> (<code>fr0</code> to <code>fr63</code>). 
Odd registers are excluded not in the class but through the use of a machine
mode larger than 4 bytes.

          <br><dt><code>l</code>
          <dd>Register in the class <code>LR_REG</code> (the <code>lr</code> register).

          <br><dt><code>q</code>
          <dd>Register in the class <code>QUAD_REGS</code> (<code>gr2</code> to <code>gr63</code>). 
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.

          <br><dt><code>t</code>
          <dd>Register in the class <code>ICC_REGS</code> (<code>icc0</code> to <code>icc3</code>).

          <br><dt><code>u</code>
          <dd>Register in the class <code>FCC_REGS</code> (<code>fcc0</code> to <code>fcc3</code>).

          <br><dt><code>v</code>
          <dd>Register in the class <code>ICR_REGS</code> (<code>cc4</code> to <code>cc7</code>).

          <br><dt><code>w</code>
          <dd>Register in the class <code>FCR_REGS</code> (<code>cc0</code> to <code>cc3</code>).

          <br><dt><code>x</code>
          <dd>Register in the class <code>QUAD_FPR_REGS</code> (<code>fr0</code> to <code>fr63</code>). 
Register numbers not divisible by 4 are excluded not in the class but through
the use of a machine mode larger than 8 bytes.

          <br><dt><code>z</code>
          <dd>Register in the class <code>SPR_REGS</code> (<code>lcr</code> and <code>lr</code>).

          <br><dt><code>A</code>
          <dd>Register in the class <code>QUAD_ACC_REGS</code> (<code>acc0</code> to <code>acc7</code>).

          <br><dt><code>B</code>
          <dd>Register in the class <code>ACCG_REGS</code> (<code>accg0</code> to <code>accg7</code>).

          <br><dt><code>C</code>
          <dd>Register in the class <code>CR_REGS</code> (<code>cc0</code> to <code>cc7</code>).

          <br><dt><code>G</code>
          <dd>Floating point constant zero

          <br><dt><code>I</code>
          <dd>6-bit signed integer constant

          <br><dt><code>J</code>
          <dd>10-bit signed integer constant

          <br><dt><code>L</code>
          <dd>16-bit signed integer constant

          <br><dt><code>M</code>
          <dd>16-bit unsigned integer constant

          <br><dt><code>N</code>
          <dd>12-bit signed integer constant that is negative--i.e. in the
range of -2048 to -1

          <br><dt><code>O</code>
          <dd>Constant zero

          <br><dt><code>P</code>
          <dd>12-bit signed integer constant that is greater than zero--i.e. in the
range of 1 to 2047.

     </dl>

     <br><dt><em>IP2K--</em><code>ip2k.h</code><em></em>
     <dd>
          <dl>
<dt><code>a</code>
          <dd><code>DP</code> or <code>IP</code> registers (general address)

          <br><dt><code>f</code>
          <dd><code>IP</code> register

          <br><dt><code>j</code>
          <dd><code>IPL</code> register

          <br><dt><code>k</code>
          <dd><code>IPH</code> register

          <br><dt><code>b</code>
          <dd><code>DP</code> register

          <br><dt><code>y</code>
          <dd><code>DPH</code> register

          <br><dt><code>z</code>
          <dd><code>DPL</code> register

          <br><dt><code>q</code>
          <dd><code>SP</code> register

          <br><dt><code>c</code>
          <dd><code>DP</code> or <code>SP</code> registers (offsettable address)

          <br><dt><code>d</code>
          <dd>Non-pointer registers (not <code>SP</code>, <code>DP</code>, <code>IP</code>)

          <br><dt><code>u</code>
          <dd>Non-SP registers (everything except <code>SP</code>)

          <br><dt><code>R</code>
          <dd>Indirect thru <code>IP</code> - Avoid this except for <code>QImode</code>, since we
can't access extra bytes

          <br><dt><code>S</code>
          <dd>Indirect thru <code>SP</code> or <code>DP</code> with short displacement (0..127)

          <br><dt><code>T</code>
          <dd>Data-section immediate value

          <br><dt><code>I</code>
          <dd>Integers from -255 to -1

          <br><dt><code>J</code>
          <dd>Integers from 0 to 7--valid bit number in a register

          <br><dt><code>K</code>
          <dd>Integers from 0 to 127--valid displacement for addressing mode

          <br><dt><code>L</code>
          <dd>Integers from 1 to 127

          <br><dt><code>M</code>
          <dd>Integer -1

          <br><dt><code>N</code>
          <dd>Integer 1

          <br><dt><code>O</code>
          <dd>Zero

          <br><dt><code>P</code>
          <dd>Integers from 0 to 255
</dl>

     <br><dt><em>MIPS--</em><code>mips.h</code><em></em>
     <dd>
          <dl>
<dt><code>d</code>
          <dd>General-purpose integer register

          <br><dt><code>f</code>
          <dd>Floating-point register (if available)

          <br><dt><code>h</code>
          <dd><code>Hi</code> register

          <br><dt><code>l</code>
          <dd><code>Lo</code> register

          <br><dt><code>x</code>
          <dd><code>Hi</code> or <code>Lo</code> register

          <br><dt><code>y</code>
          <dd>General-purpose integer register

          <br><dt><code>z</code>
          <dd>Floating-point status register

          <br><dt><code>I</code>
          <dd>Signed 16-bit constant (for arithmetic instructions)

          <br><dt><code>J</code>
          <dd>Zero

          <br><dt><code>K</code>
          <dd>Zero-extended 16-bit constant (for logic instructions)

          <br><dt><code>L</code>
          <dd>Constant with low 16 bits zero (can be loaded with <code>lui</code>)

          <br><dt><code>M</code>
          <dd>32-bit constant which requires two instructions to load (a constant
which is not <code>I</code>, <code>K</code>, or <code>L</code>)

          <br><dt><code>N</code>
          <dd>Negative 16-bit constant

          <br><dt><code>O</code>
          <dd>Exact power of two

          <br><dt><code>P</code>
          <dd>Positive 16-bit constant

          <br><dt><code>G</code>
          <dd>Floating point zero

          <br><dt><code>Q</code>
          <dd>Memory reference that can be loaded with more than one instruction
(<code>m</code> is preferable for <code>asm</code> statements)

          <br><dt><code>R</code>
          <dd>Memory reference that can be loaded with one instruction
(<code>m</code> is preferable for <code>asm</code> statements)

          <br><dt><code>S</code>
          <dd>Memory reference in external OSF/rose PIC format
(<code>m</code> is preferable for <code>asm</code> statements)
</dl>

     <br><dt><em>Motorola 680x0--</em><code>m68k.h</code><em></em>
     <dd>
          <dl>
<dt><code>a</code>
          <dd>Address register

          <br><dt><code>d</code>
          <dd>Data register

          <br><dt><code>f</code>
          <dd>68881 floating-point register, if available

          <br><dt><code>x</code>
          <dd>Sun FPA (floating-point) register, if available

          <br><dt><code>y</code>
          <dd>First 16 Sun FPA registers, if available

          <br><dt><code>I</code>
          <dd>Integer in the range 1 to 8

          <br><dt><code>J</code>
          <dd>16-bit signed number

          <br><dt><code>K</code>
          <dd>Signed number whose magnitude is greater than 0x80