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<h3 class="section">Using vector instructions through built-in functions</h3>



   <p>On some targets, the instruction set contains SIMD vector instructions that

operate on multiple values contained in one large register at the same time. 

For example, on the i386 the MMX, 3Dnow! and SSE extensions can be used

this way.



   <p>The first step in using these extensions is to provide the necessary data

types.  This should be done using an appropriate <code>typedef</code>:



<pre class="example">     typedef int v4si __attribute__ ((mode(V4SI)));

     </pre>



   <p>The base type <code>int</code> is effectively ignored by the compiler, the

actual properties of the new type <code>v4si</code> are defined by the

<code>__attribute__</code>.  It defines the machine mode to be used; for vector

types these have the form <code>V</code><var>n</var><code></code><var>B</var><code></code>; <var>n</var> should be the

number of elements in the vector, and <var>B</var> should be the base mode of the

individual elements.  The following can be used as base modes:



     <dl>

<dt><code>QI</code>

     <dd>An integer that is as wide as the smallest addressable unit, usually 8 bits. 

<br><dt><code>HI</code>

     <dd>An integer, twice as wide as a QI mode integer, usually 16 bits. 

<br><dt><code>SI</code>

     <dd>An integer, four times as wide as a QI mode integer, usually 32 bits. 

<br><dt><code>DI</code>

     <dd>An integer, eight times as wide as a QI mode integer, usually 64 bits. 

<br><dt><code>SF</code>

     <dd>A floating point value, as wide as a SI mode integer, usually 32 bits. 

<br><dt><code>DF</code>

     <dd>A floating point value, as wide as a DI mode integer, usually 64 bits. 

</dl>



   <p>Specifying a combination that is not valid for the current architecture

will cause gcc to synthesize the instructions using a narrower mode. 

For example, if you specify a variable of type <code>V4SI</code> and your

architecture does not allow for this specific SIMD type, gcc will

produce code that uses 4 <code>SIs</code>.



   <p>The types defined in this manner can be used with a subset of normal C

operations.  Currently, gcc will allow using the following operators on

these types: <code>+, -, *, /, unary minus</code>.



   <p>The operations behave like C++ <code>valarrays</code>.  Addition is defined as

the addition of the corresponding elements of the operands.  For

example, in the code below, each of the 4 elements in <var>a</var> will be

added to the corresponding 4 elements in <var>b</var> and the resulting

vector will be stored in <var>c</var>.



<pre class="example">     typedef int v4si __attribute__ ((mode(V4SI)));

     

     v4si a, b, c;

     

     c = a + b;

     </pre>



   <p>Subtraction, multiplication, and division operate in a similar manner. 

Likewise, the result of using the unary minus operator on a vector type

is a vector whose elements are the negative value of the corresponding

elements in the operand.



   <p>You can declare variables and use them in function calls and returns, as

well as in assignments and some casts.  You can specify a vector type as

a return type for a function.  Vector types can also be used as function

arguments.  It is possible to cast from one vector type to another,

provided they are of the same size (in fact, you can also cast vectors

to and from other datatypes of the same size).



   <p>You cannot operate between vectors of different lengths or different

signedness without a cast.



   <p>A port that supports hardware vector operations, usually provides a set

of built-in functions that can be used to operate on vectors.  For

example, a function to add two vectors and multiply the result by a

third could look like this:



<pre class="example">     v4si f (v4si a, v4si b, v4si c)

     {

       v4si tmp = __builtin_addv4si (a, b);

       return __builtin_mulv4si (tmp, c);

     }

     

     </pre>



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