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<h4 class="subsection">ARM Options</h4>
<p>These <code>-m</code> options are defined for Advanced RISC Machines (ARM)
architectures:
<dl>
<dt><code>-mapcs-frame</code>
<dd>Generate a stack frame that is compliant with the ARM Procedure Call
Standard for all functions, even if this is not strictly necessary for
correct execution of the code. Specifying <code>-fomit-frame-pointer</code>
with this option will cause the stack frames not to be generated for
leaf functions. The default is <code>-mno-apcs-frame</code>.
<br><dt><code>-mapcs</code>
<dd>This is a synonym for <code>-mapcs-frame</code>.
<br><dt><code>-mapcs-26</code>
<dd>Generate code for a processor running with a 26-bit program counter,
and conforming to the function calling standards for the APCS 26-bit
option. This option replaces the <code>-m2</code> and <code>-m3</code> options
of previous releases of the compiler.
<br><dt><code>-mapcs-32</code>
<dd>Generate code for a processor running with a 32-bit program counter,
and conforming to the function calling standards for the APCS 32-bit
option. This option replaces the <code>-m6</code> option of previous releases
of the compiler.
<br><dt><code>-mthumb-interwork</code>
<dd>Generate code which supports calling between the ARM and Thumb
instruction sets. Without this option the two instruction sets cannot
be reliably used inside one program. The default is
<code>-mno-thumb-interwork</code>, since slightly larger code is generated
when <code>-mthumb-interwork</code> is specified.
<br><dt><code>-mno-sched-prolog</code>
<dd>Prevent the reordering of instructions in the function prolog, or the
merging of those instruction with the instructions in the function's
body. This means that all functions will start with a recognizable set
of instructions (or in fact one of a choice from a small set of
different function prologues), and this information can be used to
locate the start if functions inside an executable piece of code. The
default is <code>-msched-prolog</code>.
<br><dt><code>-mhard-float</code>
<dd>Generate output containing floating point instructions. This is the
default.
<br><dt><code>-msoft-float</code>
<dd>Generate output containing library calls for floating point.
<strong>Warning:</strong> the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation. You must make
your own arrangements to provide suitable library functions for
cross-compilation.
<p><code>-msoft-float</code> changes the calling convention in the output file;
therefore, it is only useful if you compile <em>all</em> of a program with
this option. In particular, you need to compile <code>libgcc.a</code>, the
library that comes with GCC, with <code>-msoft-float</code> in order for
this to work.
<br><dt><code>-mlittle-endian</code>
<dd>Generate code for a processor running in little-endian mode. This is
the default for all standard configurations.
<br><dt><code>-mbig-endian</code>
<dd>Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
<br><dt><code>-mwords-little-endian</code>
<dd>This option only applies when generating code for big-endian processors.
Generate code for a little-endian word order but a big-endian byte
order. That is, a byte order of the form <code>32107654</code>. Note: this
option should only be used if you require compatibility with code for
big-endian ARM processors generated by versions of the compiler prior to
2.8.
<br><dt><code>-malignment-traps</code>
<dd>Generate code that will not trap if the MMU has alignment traps enabled.
On ARM architectures prior to ARMv4, there were no instructions to
access half-word objects stored in memory. However, when reading from
memory a feature of the ARM architecture allows a word load to be used,
even if the address is unaligned, and the processor core will rotate the
data as it is being loaded. This option tells the compiler that such
misaligned accesses will cause a MMU trap and that it should instead
synthesize the access as a series of byte accesses. The compiler can
still use word accesses to load half-word data if it knows that the
address is aligned to a word boundary.
<p>This option is ignored when compiling for ARM architecture 4 or later,
since these processors have instructions to directly access half-word
objects in memory.
<br><dt><code>-mno-alignment-traps</code>
<dd>Generate code that assumes that the MMU will not trap unaligned
accesses. This produces better code when the target instruction set
does not have half-word memory operations (i.e. implementations prior to
ARMv4).
<p>Note that you cannot use this option to access unaligned word objects,
since the processor will only fetch one 32-bit aligned object from
memory.
<p>The default setting for most targets is <code>-mno-alignment-traps</code>, since
this produces better code when there are no half-word memory
instructions available.
<br><dt><code>-mshort-load-bytes</code>
<dd><dt><code>-mno-short-load-words</code>
<dd>These are deprecated aliases for <code>-malignment-traps</code>.
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