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<h4 class="subsection">M88K Options</h4>
<p>These <code>-m</code> options are defined for Motorola 88k architectures:
<dl>
<dt><code>-m88000</code>
<dd>Generate code that works well on both the m88100 and the
m88110.
<br><dt><code>-m88100</code>
<dd>Generate code that works best for the m88100, but that also
runs on the m88110.
<br><dt><code>-m88110</code>
<dd>Generate code that works best for the m88110, and may not run
on the m88100.
<br><dt><code>-mbig-pic</code>
<dd>Obsolete option to be removed from the next revision.
Use <code>-fPIC</code>.
<br><dt><code>-midentify-revision</code>
<dd>Include an <code>ident</code> directive in the assembler output recording the
source file name, compiler name and version, timestamp, and compilation
flags used.
<br><dt><code>-mno-underscores</code>
<dd>In assembler output, emit symbol names without adding an underscore
character at the beginning of each name. The default is to use an
underscore as prefix on each name.
<br><dt><code>-mocs-debug-info</code>
<dd><dt><code>-mno-ocs-debug-info</code>
<dd>Include (or omit) additional debugging information (about registers used
in each stack frame) as specified in the 88open Object Compatibility
Standard, "OCS". This extra information allows debugging of code that
has had the frame pointer eliminated. The default for SVr4 and Delta 88
SVr3.2 is to include this information; other 88k configurations omit this
information by default.
<br><dt><code>-mocs-frame-position</code>
<dd>When emitting COFF debugging information for automatic variables and
parameters stored on the stack, use the offset from the canonical frame
address, which is the stack pointer (register 31) on entry to the
function. The SVr4 and Delta88 SVr3.2, and BCS configurations use
<code>-mocs-frame-position</code>; other 88k configurations have the default
<code>-mno-ocs-frame-position</code>.
<br><dt><code>-mno-ocs-frame-position</code>
<dd>When emitting COFF debugging information for automatic variables and
parameters stored on the stack, use the offset from the frame pointer
register (register 30). When this option is in effect, the frame
pointer is not eliminated when debugging information is selected by the
-g switch.
<br><dt><code>-moptimize-arg-area</code>
<dd>Save space by reorganizing the stack frame. This option generates code
that does not agree with the 88open specifications, but uses less
memory.
<dt><code>-mno-optimize-arg-area</code>
<dd>Do not reorganize the stack frame to save space. This is the default.
The generated conforms to the specification, but uses more memory.
<br><dt><code>-mshort-data-</code><var>num</var><code></code>
<dd>Generate smaller data references by making them relative to <code>r0</code>,
which allows loading a value using a single instruction (rather than the
usual two). You control which data references are affected by
specifying <var>num</var> with this option. For example, if you specify
<code>-mshort-data-512</code>, then the data references affected are those
involving displacements of less than 512 bytes.
<code>-mshort-data-</code><var>num</var><code></code> is not effective for <var>num</var> greater
than 64k.
<br><dt><code>-mserialize-volatile</code>
<dd><dt><code>-mno-serialize-volatile</code>
<dd>Do, or don't, generate code to guarantee sequential consistency
of volatile memory references. By default, consistency is
guaranteed.
<p>The order of memory references made by the MC88110 processor does
not always match the order of the instructions requesting those
references. In particular, a load instruction may execute before
a preceding store instruction. Such reordering violates
sequential consistency of volatile memory references, when there
are multiple processors. When consistency must be guaranteed,
GCC generates special instructions, as needed, to force
execution in the proper order.
<p>The MC88100 processor does not reorder memory references and so
always provides sequential consistency. However, by default, GCC
generates the special instructions to guarantee consistency
even when you use <code>-m88100</code>, so that the code may be run on an
MC88110 processor. If you intend to run your code only on the
MC88100 processor, you may use <code>-mno-serialize-volatile</code>.
<p>The extra code generated to guarantee consistency may affect the
performance of your application. If you know that you can safely
forgo this guarantee, you may use <code>-mno-serialize-volatile</code>.
<br><dt><code>-msvr4</code>
<dd><dt><code>-msvr3</code>
<dd>Turn on (<code>-msvr4</code>) or off (<code>-msvr3</code>) compiler extensions
related to System V release 4 (SVr4). This controls the following:
<ol type=1 start=1>
<li>Which variant of the assembler syntax to emit.
<li><code>-msvr4</code> makes the C preprocessor recognize <code>#pragma weak</code>
that is used on System V release 4.
<li><code>-msvr4</code> makes GCC issue additional declaration directives used in
SVr4.
</ol>
<p><code>-msvr4</code> is the default for the m88k-motorola-sysv4 configuration.
<code>-msvr3</code> is the default for all other m88k configurations.
<br><dt><code>-mversion-03.00</code>
<dd>This option is obsolete, and is ignored.
<br><dt><code>-mno-check-zero-division</code>
<dd><dt><code>-mcheck-zero-division</code>
<dd>Do, or don't, generate code to guarantee that integer division by
zero will be detected. By default, detection is guaranteed.
<p>Some models of the MC88100 processor fail to trap upon integer
division by zero under certain conditions. By default, when
compiling code that might be run on such a processor, GCC
generates code that explicitly checks for zero-valued divisors
and traps with exception number 503 when one is detected. Use of
<code>-mno-check-zero-division</code> suppresses such checking for code
generated to run on an MC88100 processor.
<p>GCC assumes that the MC88110 processor correctly detects all instances
of integer division by zero. When <code>-m88110</code> is specified, no
explicit checks for zero-valued divisors are generated, and both
<code>-mcheck-zero-division</code> and <code>-mno-check-zero-division</code> are
ignored.
<br><dt><code>-muse-div-instruction</code>
<dd>Use the div instruction for signed integer division on the
MC88100 processor. By default, the div instruction is not used.
<p>On the MC88100 processor the signed integer division instruction
div) traps to the operating system on a negative operand. The
operating system transparently completes the operation, but at a
large cost in execution time. By default, when compiling code
that might be run on an MC88100 processor, GCC emulates signed
integer division using the unsigned integer division instruction
divu), thereby avoiding the large penalty of a trap to the
operating system. Such emulation has its own, smaller, execution
cost in both time and space. To the extent that your code's
important signed integer division operations are performed on two
nonnegative operands, it may be desirable to use the div
instruction directly.
<p>On the MC88110 processor the div instruction (also known as the
divs instruction) processes negative operands without trapping to
the operating system. When <code>-m88110</code> is specified,
<code>-muse-div-instruction</code> is ignored, and the div instruction is used
for signed integer division.
<p>Note that the result of dividing <code>INT_MIN</code> by -1 is undefined. In
particular, the behavior of such a division with and without
<code>-muse-div-instruction</code> may differ.
<br><dt><code>-mtrap-large-shift</code>
<dd><dt><code>-mhandle-large-shift</code>
<dd>Include code to detect bit-shifts of more than 31 bits; respectively,
trap such shifts or emit code to handle them properly. By default GCC
makes no special provision for large bit shifts.
<br><dt><code>-mwarn-passed-structs</code>
<dd>Warn when a function passes a struct as an argument or result.
Structure-passing conventions have changed during the evolution of the C
language, and are often the source of portability problems. By default,
GCC issues no such warning.
</dl>
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