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Node:<a name="ARM%20Opcodes">ARM Opcodes</a>,

Previous:<a rel="previous" accesskey="p" href="ARM-Directives.html#ARM%20Directives">ARM Directives</a>,

Up:<a rel="up" accesskey="u" href="ARM-Dependent.html#ARM-Dependent">ARM-Dependent</a>

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<h4 class="section">Opcodes</h4>



   <p><code>as</code> implements all the standard ARM opcodes.  It also

implements several pseudo opcodes, including several synthetic load

instructions.



     <dl>



     <br><dt><code>NOP</code>

     <dd>

     <pre class="smallexample">            nop

          </pre>



     <p>This pseudo op will always evaluate to a legal ARM instruction that does

nothing.  Currently it will evaluate to MOV r0, r0.



     <br><dt><code>LDR</code>

     <dd>

     <pre class="smallexample">            ldr &lt;register&gt; , = &lt;expression&gt;

          </pre>



     <p>If expression evaluates to a numeric constant then a MOV or MVN

instruction will be used in place of the LDR instruction, if the

constant can be generated by either of these instructions.  Otherwise

the constant will be placed into the nearest literal pool (if it not

already there) and a PC relative LDR instruction will be generated.



     <br><dt><code>ADR</code>

     <dd>

     <pre class="smallexample">            adr &lt;register&gt; &lt;label&gt;

          </pre>



     <p>This instruction will load the address of <var>label</var> into the indicated

register.  The instruction will evaluate to a PC relative ADD or SUB

instruction depending upon where the label is located.  If the label is

out of range, or if it is not defined in the same file (and section) as

the ADR instruction, then an error will be generated.  This instruction

will not make use of the literal pool.



     <br><dt><code>ADRL</code>

     <dd>

     <pre class="smallexample">            adrl &lt;register&gt; &lt;label&gt;

          </pre>



     <p>This instruction will load the address of <var>label</var> into the indicated

register.  The instruction will evaluate to one or two PC relative ADD

or SUB instructions depending upon where the label is located.  If a

second instruction is not needed a NOP instruction will be generated in

its place, so that this instruction is always 8 bytes long.



     <p>If the label is out of range, or if it is not defined in the same file

(and section) as the ADRL instruction, then an error will be generated. 

This instruction will not make use of the literal pool.



   </dl>



   <p>For information on the ARM or Thumb instruction sets, see <cite>ARM

Software Development Toolkit Reference Manual</cite>, Advanced RISC Machines

Ltd.



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