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<h4 class="section">Memory References</h4>
<p>An Intel syntax indirect memory reference of the form
<pre class="smallexample"> <var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
</pre>
<p>is translated into the AT&T syntax
<pre class="smallexample"> <var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
</pre>
<p>where <var>base</var> and <var>index</var> are the optional 32-bit base and
index registers, <var>disp</var> is the optional displacement, and
<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
to calculate the address of the operand. If no <var>scale</var> is
specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax <em>must</em>
be preceded by a <code>%</code>. If you specify a section override which
coincides with the default section register, <code>as</code> does <em>not</em>
output any section register override prefixes to assemble the given
instruction. Thus, section overrides can be specified to emphasize which
section register is used for a given memory operand.
<p>Here are some examples of Intel and AT&T style memory references:
<dl>
<dt>AT&T: <code>-4(%ebp)</code>, Intel: <code>[ebp - 4]</code>
<dd><var>base</var> is <code>%ebp</code>; <var>disp</var> is <code>-4</code>. <var>section</var> is
missing, and the default section is used (<code>%ss</code> for addressing with
<code>%ebp</code> as the base register). <var>index</var>, <var>scale</var> are both missing.
<br><dt>AT&T: <code>foo(,%eax,4)</code>, Intel: <code>[foo + eax*4]</code>
<dd><var>index</var> is <code>%eax</code> (scaled by a <var>scale</var> 4); <var>disp</var> is
<code>foo</code>. All other fields are missing. The section register here
defaults to <code>%ds</code>.
<br><dt>AT&T: <code>foo(,1)</code>; Intel <code>[foo]</code>
<dd>This uses the value pointed to by <code>foo</code> as a memory operand.
Note that <var>base</var> and <var>index</var> are both missing, but there is only
<em>one</em> <code>,</code>. This is a syntactic exception.
<br><dt>AT&T: <code>%gs:foo</code>; Intel <code>gs:foo</code>
<dd>This selects the contents of the variable <code>foo</code> with section
register <var>section</var> being <code>%gs</code>.
</dl>
<p>Absolute (as opposed to PC relative) call and jump operands must be
prefixed with <code>*</code>. If no <code>*</code> is specified, <code>as</code>
always chooses PC relative addressing for jump/call labels.
<p>Any instruction that has a memory operand, but no register operand,
<em>must</em> specify its size (byte, word, long, or quadruple) with an
instruction mnemonic suffix (<code>b</code>, <code>w</code>, <code>l</code> or <code>q</code>,
respectively).
<p>The x86-64 architecture adds an RIP (instruction pointer relative)
addressing. This addressing mode is specified by using <code>rip</code> as a
base register. Only constant offsets are valid. For example:
<dl>
<dt>AT&T: <code>1234(%rip)</code>, Intel: <code>[rip + 1234]</code>
<dd>Points to the address 1234 bytes past the end of the current
instruction.
<br><dt>AT&T: <code>symbol(%rip)</code>, Intel: <code>[rip + symbol]</code>
<dd>Points to the <code>symbol</code> in RIP relative way, this is shorter than
the default absolute addressing.
</dl>
<p>Other addressing modes remain unchanged in x86-64 architecture, except
registers used are 64-bit instead of 32-bit.
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