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Node:<a name="M68K-Moto-Syntax">M68K-Moto-Syntax</a>,

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<h4 class="section">Motorola Syntax</h4>



   <p>The standard Motorola syntax for this chip differs from the syntax

already discussed (see <a href="M68K-Syntax.html#M68K-Syntax">Syntax</a>).  <code>as</code> can

accept Motorola syntax for operands, even if <small>MIT</small> syntax is used for

other operands in the same instruction.  The two kinds of syntax are

fully compatible.



   <p>In the following table <var>apc</var> stands for any of the address registers

(<code>%a0</code> through <code>%a7</code>), the program counter (<code>%pc</code>), the

zero-address relative to the program counter (<code>%zpc</code>), or a

suppressed address register (<code>%za0</code> through <code>%za7</code>).  The use

of <var>size</var> means one of <code>w</code> or <code>l</code>, and it may always be

omitted along with the leading dot.  The use of <var>scale</var> means one of

<code>1</code>, <code>2</code>, <code>4</code>, or <code>8</code>, and it may always be omitted

along with the leading asterisk.



   <p>The following additional addressing modes are understood:



     <dl>

<dt><dfn>Address Register Indirect</dfn>

     <dd><code>(%a0)</code> through <code>(%a7)</code><br>

<code>%a7</code> is also known as <code>%sp</code>, i.e. the Stack Pointer.  <code>%a6</code>

is also known as <code>%fp</code>, the Frame Pointer.



     <br><dt><dfn>Address Register Postincrement</dfn>

     <dd><code>(%a0)+</code> through <code>(%a7)+</code>



     <br><dt><dfn>Address Register Predecrement</dfn>

     <dd><code>-(%a0)</code> through <code>-(%a7)</code>



     <br><dt><dfn>Indirect Plus Offset</dfn>

     <dd><code></code><var>number</var><code>(</code><var>%a0</var><code>)</code> through <code></code><var>number</var><code>(</code><var>%a7</var><code>)</code>,

or <code></code><var>number</var><code>(</code><var>%pc</var><code>)</code>.



     <p>The <var>number</var> may also appear within the parentheses, as in

<code>(</code><var>number</var><code>,</code><var>%a0</var><code>)</code>.  When used with the <var>pc</var>, the

<var>number</var> may be omitted (with an address register, omitting the

<var>number</var> produces Address Register Indirect mode).



     <br><dt><dfn>Index</dfn>

     <dd><code></code><var>number</var><code>(</code><var>apc</var><code>,</code><var>register</var><code>.</code><var>size</var><code>*</code><var>scale</var><code>)</code>



     <p>The <var>number</var> may be omitted, or it may appear within the

parentheses.  The <var>apc</var> may be omitted.  The <var>register</var> and the

<var>apc</var> may appear in either order.  If both <var>apc</var> and

<var>register</var> are address registers, and the <var>size</var> and <var>scale</var>

are omitted, then the first register is taken as the base register, and

the second as the index register.



     <br><dt><dfn>Postindex</dfn>

     <dd><code>([</code><var>number</var><code>,</code><var>apc</var><code>],</code><var>register</var><code>.</code><var>size</var><code>*</code><var>scale</var><code>,</code><var>onumber</var><code>)</code>



     <p>The <var>onumber</var>, or the <var>register</var>, or both, may be omitted. 

Either the <var>number</var> or the <var>apc</var> may be omitted, but not both.



     <br><dt><dfn>Preindex</dfn>

     <dd><code>([</code><var>number</var><code>,</code><var>apc</var><code>,</code><var>register</var><code>.</code><var>size</var><code>*</code><var>scale</var><code>],</code><var>onumber</var><code>)</code>



     <p>The <var>number</var>, or the <var>apc</var>, or the <var>register</var>, or any two of

them, may be omitted.  The <var>onumber</var> may be omitted.  The

<var>register</var> and the <var>apc</var> may appear in either order.  If both

<var>apc</var> and <var>register</var> are address registers, and the <var>size</var>

and <var>scale</var> are omitted, then the first register is taken as the

base register, and the second as the index register. 

</dl>



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