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   <p>The following options are available when as is configured for the
Intel 80960 processor.

     <dl>
<dt><code>-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC</code>
     <dd>Specify which variant of the 960 architecture is the target.

     <br><dt><code>-b</code>
     <dd>Add code to collect statistics about branches taken.

     <br><dt><code>-no-relax</code>
     <dd>Do not alter compare-and-branch instructions for long displacements;
error if necessary.

   </dl>

   <p>The following options are available when as is configured for the
Mitsubishi M32R series.

     <dl>

     <br><dt><code>--m32rx</code>
     <dd>Specify which processor in the M32R family is the target.  The default
is normally the M32R, but this option changes it to the M32RX.

     <br><dt><code>--warn-explicit-parallel-conflicts or --Wp</code>
     <dd>Produce warning messages when questionable parallel constructs are
encountered.

     <br><dt><code>--no-warn-explicit-parallel-conflicts or --Wnp</code>
     <dd>Do not produce warning messages when questionable parallel constructs are
encountered.

   </dl>

   <p>The following options are available when as is configured for the
Motorola 68000 series.

     <dl>

     <br><dt><code>-l</code>
     <dd>Shorten references to undefined symbols, to one word instead of two.

     <br><dt><code>-m68000 | -m68008 | -m68010 | -m68020 | -m68030</code>
     <dd><dt><code>| -m68040 | -m68060 | -m68302 | -m68331 | -m68332</code>
     <dd><dt><code>| -m68333 | -m68340 | -mcpu32 | -m5200</code>
     <dd>Specify what processor in the 68000 family is the target.  The default
is normally the 68020, but this can be changed at configuration time.

     <br><dt><code>-m68881 | -m68882 | -mno-68881 | -mno-68882</code>
     <dd>The target machine does (or does not) have a floating-point coprocessor. 
The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
the basic 68000 is not compatible with the 68881, a combination of the
two can be specified, since it's possible to do emulation of the
coprocessor instructions with the main processor.

     <br><dt><code>-m68851 | -mno-68851</code>
     <dd>The target machine does (or does not) have a memory-management
unit coprocessor.  The default is to assume an MMU for 68020 and up.

   </dl>

   <p>For details about the PDP-11 machine dependent features options,
see <a href="PDP-11-Options.html#PDP-11-Options">PDP-11-Options</a>.

     <dl>
<dt><code>-mpic | -mno-pic</code>
     <dd>Generate position-independent (or position-dependent) code.  The
default is <code>-mpic</code>.

     <br><dt><code>-mall</code>
     <dd><dt><code>-mall-extensions</code>
     <dd>Enable all instruction set extensions.  This is the default.

     <br><dt><code>-mno-extensions</code>
     <dd>Disable all instruction set extensions.

     <br><dt><code>-m</code><var>extension</var><code> | -mno-</code><var>extension</var><code></code>
     <dd>Enable (or disable) a particular instruction set extension.

     <br><dt><code>-m</code><var>cpu</var><code></code>
     <dd>Enable the instruction set extensions supported by a particular CPU, and
disable all other extensions.

     <br><dt><code>-m</code><var>machine</var><code></code>
     <dd>Enable the instruction set extensions supported by a particular machine
model, and disable all other extensions. 
</dl>

   <p>The following options are available when as is configured for
a picoJava processor.

     <dl>

     <br><dt><code>-mb</code>
     <dd>Generate "big endian" format output.

     <br><dt><code>-ml</code>
     <dd>Generate "little endian" format output.

   </dl>

   <p>The following options are available when as is configured for the
Motorola 68HC11 or 68HC12 series.

     <dl>

     <br><dt><code>-m68hc11 | -m68hc12</code>
     <dd>Specify what processor is the target.  The default is
defined by the configuration option when building the assembler.

     <br><dt><code>--force-long-branchs</code>
     <dd>Relative branches are turned into absolute ones. This concerns
conditional branches, unconditional branches and branches to a
sub routine.

     <br><dt><code>-S | --short-branchs</code>
     <dd>Do not turn relative branchs into absolute ones
when the offset is out of range.

     <br><dt><code>--strict-direct-mode</code>
     <dd>Do not turn the direct addressing mode into extended addressing mode
when the instruction does not support direct addressing mode.

     <br><dt><code>--print-insn-syntax</code>
     <dd>Print the syntax of instruction in case of error.

     <br><dt><code>--print-opcodes</code>
     <dd>print the list of instructions with syntax and then exit.

     <br><dt><code>--generate-example</code>
     <dd>print an example of instruction for each possible instruction and then exit. 
This option is only useful for testing <code>as</code>.

   </dl>

   <p>The following options are available when <code>as</code> is configured
for the SPARC architecture:

     <dl>
<dt><code>-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite</code>
     <dd><dt><code>-Av8plus | -Av8plusa | -Av9 | -Av9a</code>
     <dd>Explicitly select a variant of the SPARC architecture.

     <p><code>-Av8plus</code> and <code>-Av8plusa</code> select a 32 bit environment. 
<code>-Av9</code> and <code>-Av9a</code> select a 64 bit environment.

     <p><code>-Av8plusa</code> and <code>-Av9a</code> enable the SPARC V9 instruction set with
UltraSPARC extensions.

     <br><dt><code>-xarch=v8plus | -xarch=v8plusa</code>
     <dd>For compatibility with the Solaris v9 assembler.  These options are
equivalent to -Av8plus and -Av8plusa, respectively.

     <br><dt><code>-bump</code>
     <dd>Warn when the assembler switches to another architecture. 
</dl>

   <p>The following options are available when as is configured for
a <small>MIPS</small> processor.

     <dl>
<dt><code>-G </code><var>num</var><code></code>
     <dd>This option sets the largest size of an object that can be referenced
implicitly with the <code>gp</code> register.  It is only accepted for targets that
use ECOFF format, such as a DECstation running Ultrix.  The default value is 8.

     <br><dt><code>-EB</code>
     <dd>Generate "big endian" format output.

     <br><dt><code>-EL</code>
     <dd>Generate "little endian" format output.

     <br><dt><code>-mips1</code>
     <dd><dt><code>-mips2</code>
     <dd><dt><code>-mips3</code>
     <dd><dt><code>-mips4</code>
     <dd><dt><code>-mips5</code>
     <dd><dt><code>-mips32</code>
     <dd><dt><code>-mips64</code>
     <dd>Generate code for a particular <small>MIPS</small> Instruction Set Architecture level. 
<code>-mips1</code> is an alias for <code>-march=r3000</code>, <code>-mips2</code> is an
alias for <code>-march=r6000</code>, <code>-mips3</code> is an alias for
<code>-march=r4000</code> and <code>-mips4</code> is an alias for <code>-march=r8000</code>. 
<code>-mips5</code>, <code>-mips32</code>, and <code>-mips64</code> correspond to generic
<code>MIPS V</code>, <code>MIPS32</code>, and <code>MIPS64</code> ISA processors,
respectively.

     <br><dt><code>-march=</code><var>CPU</var><code></code>
     <dd>Generate code for a particular <small>MIPS</small> cpu.

     <br><dt><code>-mtune=</code><var>cpu</var><code></code>
     <dd>Schedule and tune for a particular <small>MIPS</small> cpu.

     <br><dt><code>-mfix7000</code>
     <dd><dt><code>-mno-fix7000</code>
     <dd>Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.

     <br><dt><code>-mdebug</code>
     <dd><dt><code>-no-mdebug</code>
     <dd>Cause stabs-style debugging output to go into an ECOFF-style .mdebug
section instead of the standard ELF .stabs sections.

     <br><dt><code>-mgp32</code>
     <dd><dt><code>-mfp32</code>
     <dd>The register sizes are normally inferred from the ISA and ABI, but these
flags force a certain group of registers to be treated as 32 bits wide at
all times.  <code>-mgp32</code> controls the size of general-purpose registers
and <code>-mfp32</code> controls the size of floating-point registers.

     <br><dt><code>-mips16</code>
     <dd><dt><code>-no-mips16</code>
     <dd>Generate code for the MIPS 16 processor.  This is equivalent to putting
<code>.set mips16</code> at the start of the assembly file.  <code>-no-mips16</code>
turns off this option.

     <br><dt><code>-mips3d</code>
     <dd><dt><code>-no-mips3d</code>
     <dd>Generate code for the MIPS-3D Application Specific Extension. 
This tells the assembler to accept MIPS-3D instructions. 
<code>-no-mips3d</code> turns off this option.

     <br><dt><code>-mdmx</code>
     <dd><dt><code>-no-mdmx</code>
     <dd>Generate code for the MDMX Application Specific Extension. 
This tells the assembler to accept MDMX instructions. 
<code>-no-mdmx</code> turns off this option.

     <br><dt><code>--construct-floats</code>
     <dd><dt><code>--no-construct-floats</code>
     <dd>The <code>--no-construct-floats</code> option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register.  By default <code>--construct-floats</code> is
selected, allowing construction of these floating point constants.

     <br><dt><code>--emulation=</code><var>name</var><code></code>
     <dd>This option causes <code>as</code> to emulate <code>as</code> configured
for some other target, in all respects, including output format (choosing
between ELF and ECOFF only), handling of pseudo-opcodes which may generate
debugging information or store symbol table information, and default
endianness.  The available configuration names are: <code>mipsecoff</code>,
<code>mipself</code>, <code>mipslecoff</code>, <code>mipsbecoff</code>, <code>mipslelf</code>,
<code>mipsbelf</code>.  The first two do not alter the default endianness from that
of the primary target for which the assembler was configured; the others change
the default to little- or big-endian as indicated by the <code>b</code> or <code>l</code>
in the name.  Using <code>-EB</code> or <code>-EL</code> will override the endianness
selection in any case.

     <p>This option is currently supported only when the primary target
<code>as</code> is configured for is a <small>MIPS</small> ELF or ECOFF target. 
Furthermore, the primary target or others specified with
<code>--enable-targets=...</code> at configuration time must include support for
the other format, if both are to be available.  For example, the Irix 5
configuration includes support for both.

     <p>Eventually, this option will support more configurations, with more
fine-grained control over the assembler's behavior, and will be supported for
more processors.

     <br><dt><code>-nocpp</code>
     <dd><code>as</code> ignores this option.  It is accepted for compatibility with
the native tools.

     <br><dt><code>--trap</code>
     <dd><dt><code>--no-trap</code>
     <dd><dt><code>--break</code>
     <dd><dt><code>--no-break</code>
     <dd>Control how to deal with multiplication overflow and division by zero. 
<code>--trap</code> or <code>--no-break</code> (which are synonyms) take a trap exception
(and only work for Instruction Set Architecture level 2 and higher);
<code>--break</code> or <code>--no-trap</code> (also synonyms, and the default) take a
break exception.

     <br><dt><code>-n</code>
     <dd>When this option is used, <code>as</code> will issue a warning every
time it generates a nop instruction from a macro. 
</dl>

   <p>The following options are available when as is configured for
an MCore processor.

     <dl>
<dt><code>-jsri2bsr</code>
     <dd><dt><code>-nojsri2bsr</code>
     <dd>Enable or disable the JSRI to BSR transformation.  By default this is enabled. 
The command line option <code>-nojsri2bsr</code> can be used to disable it.

     <br><dt><code>-sifilter</code>
     <dd><dt><code>-nosifilter</code>
     <dd>Enable or disable the silicon filter behaviour.  By default this is disabled. 
The default can be overridden by the <code>-sifilter</code> command line option.

     <br><dt><code>-relax</code>
     <dd>Alter jump instructions for long displacements.

     <br><dt><code>-mcpu=[210|340]</code>
     <dd>Select the cpu type on the target hardware.  This controls which instructions
can be assembled.

     <br><dt><code>-EB</code>
     <dd>Assemble for a big endian target.

     <br><dt><code>-EL</code>
     <dd>Assemble for a little endian target.

   </dl>

   <p>See the info pages for documentation of the MMIX-specific options.

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<li><a accesskey="1" href="Manual.html#Manual">Manual</a>:                       Structure of this Manual
<li><a accesskey="2" href="GNU-Assembler.html#GNU%20Assembler">GNU Assembler</a>:                The GNU Assembler
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