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<h4 class="section">Alpha Assembler Directives</h4>
<p><code>as</code> for the Alpha supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly.
<p>These are the additional directives in <code>as</code> for the Alpha:
<dl>
<dt><code>.arch </code><var>cpu</var><code></code>
<dd>Specifies the target processor. This is equivalent to the
<code>-m</code><var>cpu</var><code></code> command-line option. See <a href="Alpha-Options.html#Alpha%20Options">Options</a>,
for a list of values for <var>cpu</var>.
<br><dt><code>.ent </code><var>function</var><code>[, </code><var>n</var><code>]</code>
<dd>Mark the beginning of <var>function</var>. An optional number may follow for
compatibility with the OSF/1 assembler, but is ignored. When generating
<code>.mdebug</code> information, this will create a procedure descriptor for
the function. In ELF, it will mark the symbol as a function a-la the
generic <code>.type</code> directive.
<br><dt><code>.end </code><var>function</var><code></code>
<dd>Mark the end of <var>function</var>. In ELF, it will set the size of the symbol
a-la the generic <code>.size</code> directive.
<br><dt><code>.mask </code><var>mask</var><code>, </code><var>offset</var><code></code>
<dd>Indicate which of the integer registers are saved in the current
function's stack frame. <var>mask</var> is interpreted a bit mask in which
bit <var>n</var> set indicates that register <var>n</var> is saved. The registers
are saved in a block located <var>offset</var> bytes from the <dfn>canonical
frame address</dfn> (CFA) which is the value of the stack pointer on entry to
the function. The registers are saved sequentially, except that the
return address register (normally <code>$26</code>) is saved first.
<p>This and the other directives that describe the stack frame are
currently only used when generating <code>.mdebug</code> information. They
may in the future be used to generate DWARF2 <code>.debug_frame</code> unwind
information for hand written assembly.
<br><dt><code>.fmask </code><var>mask</var><code>, </code><var>offset</var><code></code>
<dd>Indicate which of the floating-point registers are saved in the current
stack frame. The <var>mask</var> and <var>offset</var> parameters are interpreted
as with <code>.mask</code>.
<br><dt><code>.frame </code><var>framereg</var><code>, </code><var>frameoffset</var><code>, </code><var>retreg</var><code>[, </code><var>argoffset</var><code>]</code>
<dd>Describes the shape of the stack frame. The frame pointer in use is
<var>framereg</var>; normally this is either <code>$fp</code> or <code>$sp</code>. The
frame pointer is <var>frameoffset</var> bytes below the CFA. The return
address is initially located in <var>retreg</var> until it is saved as
indicated in <code>.mask</code>. For compatibility with OSF/1 an optional
<var>argoffset</var> parameter is accepted and ignored. It is believed to
indicate the offset from the CFA to the saved argument registers.
<br><dt><code>.prologue </code><var>n</var><code></code>
<dd>Indicate that the stack frame is set up and all registers have been
spilled. The argument <var>n</var> indicates whether and how the function
uses the incoming <dfn>procedure vector</dfn> (the address of the called
function) in <code>$27</code>. 0 indicates that <code>$27</code> is not used; 1
indicates that the first two instructions of the function use <code>$27</code>
to perform a load of the GP register; 2 indicates that <code>$27</code> is
used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
<br><dt><code>.gprel32 </code><var>expression</var><code></code>
<dd>Computes the difference between the address in <var>expression</var> and the
GP for the current object file, and stores it in 4 bytes. In addition
to being smaller than a full 8 byte address, this also does not require
a dynamic relocation when used in a shared library.
<br><dt><code>.t_floating </code><var>expression</var><code></code>
<dd>Stores <var>expression</var> as an <small>IEEE</small> double precision value.
<br><dt><code>.s_floating </code><var>expression</var><code></code>
<dd>Stores <var>expression</var> as an <small>IEEE</small> single precision value.
<br><dt><code>.f_floating </code><var>expression</var><code></code>
<dd>Stores <var>expression</var> as a VAX F format value.
<br><dt><code>.g_floating </code><var>expression</var><code></code>
<dd>Stores <var>expression</var> as a VAX G format value.
<br><dt><code>.d_floating </code><var>expression</var><code></code>
<dd>Stores <var>expression</var> as a VAX D format value.
<br><dt><code>.set </code><var>feature</var><code></code>
<dd>Enables or disables various assembler features. Using the positive
name of the feature enables while using <code>no</code><var>feature</var><code></code> disables.
<dl>
<dt><code>at</code>
<dd>Indicates that macro expansions may clobber the <dfn>assembler
temporary</dfn> (<code>$at</code> or <code>$28</code>) register. Some macros may not be
expanded without this and will generate an error message if <code>noat</code>
is in effect. When <code>at</code> is in effect, a warning will be generated
if <code>$at</code> is used by the programmer.
<br><dt><code>macro</code>
<dd>Enables the expasion of macro instructions. Note that variants of real
instructions, such as <code>br label</code> vs <code>br $31,label</code> are
considered alternate forms and not macros.
<br><dt><code>move</code>
<dd><dt><code>reorder</code>
<dd><dt><code>volatile</code>
<dd>These control whether and how the assembler may re-order instructions.
Accepted for compatibility with the OSF/1 assembler, but <code>as</code>
does not do instruction scheduling, so these features are ignored.
</dl>
</dl>
<p>The following directives are recognized for compatibility with the OSF/1
assembler but are ignored.
<pre class="example"> .proc .aproc
.reguse .livereg
.option .aent
.ugen .eflag
.alias .noalias
</pre>
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