init.s

UBOOT 源码

/*--------------------------------------------------------------------- */
/* Function:    read_spd */
/* Description: Reads contents of SPD and saves parameters to be used for */
/*		configuration in dedicated registers (see code below). */
/*---------------------------------------------------------------------	 */

#define WRITE_I2C(reg,val) \
	addi    r3,0,val;\
	addis   r4, 0, 0xef60;\
	ori     r4, r4, 0x0500 + reg;\
	stb     r3, 0(r4);\
	eieio

#define READ_I2C(reg) \
	addis   r3, 0, 0xef60;\
	ori     r3, r3, 0x0500 + reg;\
	lbz     r3, 0x0000(r3);\
	eieio

read_spd:

	mflr	r5

	/* Initialize i2c */
	/*--------------- */
	WRITE_I2C(IICLMADR, 0x00)	/* clear lo master address */
	WRITE_I2C(IICHMADR, 0x00)	/* clear hi master address */
	WRITE_I2C(IICLSADR, 0x00)	/* clear lo slave address */
	WRITE_I2C(IICHSADR, 0x00)	/* clear hi slave address */
	WRITE_I2C(IICSTS, 0x08)		/* update status register */
	WRITE_I2C(IICEXTSTS, 0x8f)
	WRITE_I2C(IICCLKDIV, 0x05)
	WRITE_I2C(IICINTRMSK, 0x00)	/* no interrupts */
	WRITE_I2C(IICXFRCNT, 0x00)	/* clear transfer count */
	WRITE_I2C(IICXTCNTLSS, 0xf0)	/* clear extended control & stat */
	WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB)	/* mode control */
	READ_I2C(IICMDCNTL)
	ori	r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
	WRITE_I2C(IICMDCNTL, r3)	/* mode control */
	WRITE_I2C(IICCNTL, 0x00)	/* clear control reg */

	/* Wait until initialization completed */
	/*------------------------------------ */
	bl	wait_i2c_transfer_done

	WRITE_I2C(IICHMADR, 0x00)	/* 7-bit addressing */
	WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)

	/* Write 0 into buffer(start address) */
	/*----------------------------------- */
	WRITE_I2C(IICMDBUF, 0x00);

	/* Wait a little */
	/*-------------- */
	addis   r3,0,0x0000
	ori     r3,r3,0xA000
	mtctr   r3
in02:	bdnz    in02

	/* Issue write command */
	/*-------------------- */
	WRITE_I2C(IICCNTL, IIC_CNTL_PT)
	bl	wait_i2c_transfer_done

	/* Read 128 bytes */
	/*--------------- */
	addi	r7, 0, 0	/* byte counter in r7 */
	addi	r8, 0, 0	/* checksum in r8 */
rdlp:
	/* issue read command */
	/*------------------- */
	cmpi	0, r7, 127
	blt	rd01
	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
	bl	rd02
rd01:	WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
rd02:	bl	wait_i2c_transfer_done

	/* Fetch byte from buffer */
	/*----------------------- */
	READ_I2C(IICMDBUF)

	/* Retrieve parameters that are going to be used during configuration. */
	/* Save them in dedicated registers. */
	/*------------------------------------------------------------ */
	cmpi	0, r7, 3	/* Save byte 3 in r10 */
	bne	rd10
	addi	r10, r3, 0
rd10:	cmpi	0, r7, 4	/* Save byte 4 in r11 */
	bne	rd11
	addi	r11, r3, 0
rd11:	cmpi	0, r7, 5	/* Save byte 5 in r12 */
	bne	rd12
	addi	r12, r3, 0
rd12:	cmpi	0, r7, 17	/* Save byte 17 in r13 */
	bne	rd13
	addi	r13, r3, 0
rd13:	cmpi	0, r7, 18	/* Save byte 18 in r14 */
	bne	rd14
	addi	r14, r3, 0
rd14:	cmpi	0, r7, 31	/* Save byte 31 in r15 */
	bne	rd15
	addi	r15, r3, 0
rd15:	cmpi	0, r7, 27	/* Save byte 27 in r16 */
	bne	rd16
	addi	r16, r3, 0
rd16:	cmpi	0, r7, 29	/* Save byte 29 in r17 */
	bne	rd17
	addi	r17, r3, 0
rd17:	cmpi	0, r7, 30	/* Save byte 30 in r18 */
	bne	rd18
	addi	r18, r3, 0
rd18:	cmpi	0, r7, 9	/* Save byte 9 in r19 */
	bne	rd19
	addi	r19, r3, 0
rd19:	cmpi	0, r7, 23	/* Save byte 23 in r20 */
	bne	rd20
	addi	r20, r3, 0
rd20:	cmpi	0, r7, 25	/* Save byte 25 in r21 */
	bne	rd21
	addi	r21, r3, 0
rd21:

	/* Calculate checksum of the first 63 bytes */
	/*----------------------------------------- */
	cmpi	0, r7, 63
	bgt	rd31
	beq	rd30
	add	r8, r8, r3
	bl	rd31

	/* Verify checksum at byte 63 */
	/*--------------------------- */
rd30:	andi.	r8, r8, 0xff		/* use only 8 bits */
	cmp	0, r8, r3
	beq	rd31
	addi	r4, 0, LED_SDRAM_CODE_8
	addis	r5, 0, 0x1000
	ori	r5, r5, 0x0001
	stb	r4,0(r5)
	eieio
rderr:	bl	rderr

rd31:

	/* Increment byte counter and check whether all bytes have been read. */
	/*------------------------------------------------------------------- */
	addi	r7, r7, 1
	cmpi	0, r7, 127
	bgt	rd05
	bl	rdlp
rd05:
	mtlr    r5                     /* restore lr */
	blr

wait_i2c_transfer_done:
	mflr	r6
wt01:	READ_I2C(IICSTS)
	andi.	r4, r3, IIC_STS_PT
	cmpi	0, r4, IIC_STS_PT
	beq	wt01
	mtlr    r6                     /* restore lr */
	blr

/*--------------------------------------------------------------------- */
/* Function:    find_mode */
/* Description: Determines addressing mode to be used dependent on   */
/*		number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
/*		byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
/*		mode is returned in r3. */
/* (It would be nicer having a table, pnc). */
/*---------------------------------------------------------------------	 */
find_mode:

	mflr	r5

	cmpi	0, r10, 11
	bne	fm01
	cmpi	0, r11, 9
	bne	fm01
	cmpi	0, r13, 2
	bne	fm01
	addi	r3, 0, 1
	bl	fmfound

fm01:	cmpi	0, r10, 11
	bne	fm02
	cmpi	0, r11, 10
	bne	fm02
	cmpi	0, r13, 2
	bne	fm02
	addi	r3, 0, 1
	bl	fmfound

fm02:	cmpi	0, r10, 12
	bne	fm03
	cmpi	0, r11, 9
	bne	fm03
	cmpi	0, r13, 4
	bne	fm03
	addi	r3, 0, 2
	bl	fmfound

fm03:	cmpi	0, r10, 12
	bne	fm04
	cmpi	0, r11, 10
	bne	fm04
	cmpi	0, r13, 4
	bne	fm04
	addi	r3, 0, 2
	bl	fmfound

fm04:	cmpi	0, r10, 13
	bne	fm05
	cmpi	0, r11, 9
	bne	fm05
	cmpi	0, r13, 4
	bne	fm05
	addi	r3, 0, 3
	bl	fmfound

fm05:	cmpi	0, r10, 13
	bne	fm06
	cmpi	0, r11, 10
	bne	fm06
	cmpi	0, r13, 4
	bne	fm06
	addi	r3, 0, 3
	bl	fmfound

fm06:	cmpi	0, r10, 13
	bne	fm07
	cmpi	0, r11, 11
	bne	fm07
	cmpi	0, r13, 4
	bne	fm07
	addi	r3, 0, 3
	bl	fmfound

fm07:	cmpi	0, r10, 12
	bne	fm08
	cmpi	0, r11, 8
	bne	fm08
	cmpi	0, r13, 2
	bne	fm08
	addi	r3, 0, 4
	bl	fmfound

fm08:	cmpi	0, r10, 12
	bne	fm09
	cmpi	0, r11, 8
	bne	fm09
	cmpi	0, r13, 4
	bne	fm09
	addi	r3, 0, 4
	bl	fmfound

fm09:	cmpi	0, r10, 11
	bne	fm10
	cmpi	0, r11, 8
	bne	fm10
	cmpi	0, r13, 2
	bne	fm10
	addi	r3, 0, 5
	bl	fmfound

fm10:	cmpi	0, r10, 11
	bne	fm11
	cmpi	0, r11, 8
	bne	fm11
	cmpi	0, r13, 4
	bne	fm11
	addi	r3, 0, 5
	bl	fmfound

fm11:	cmpi	0, r10, 13
	bne	fm12
	cmpi	0, r11, 8
	bne	fm12
	cmpi	0, r13, 2
	bne	fm12
	addi	r3, 0, 6
	bl	fmfound

fm12:	cmpi	0, r10, 13
	bne	fm13
	cmpi	0, r11, 8
	bne	fm13
	cmpi	0, r13, 4
	bne	fm13
	addi	r3, 0, 6
	bl	fmfound

fm13:	cmpi	0, r10, 13
	bne	fm14
	cmpi	0, r11, 9
	bne	fm14
	cmpi	0, r13, 2
	bne	fm14
	addi	r3, 0, 7
	bl	fmfound

fm14:	cmpi	0, r10, 13
	bne	fm15
	cmpi	0, r11, 10
	bne	fm15
	cmpi	0, r13, 2
	bne	fm15
	addi	r3, 0, 7
	bl	fmfound

fm15:
	/* not found, error code to be issued on LEDs */
	addi	r7, 0, LED_SDRAM_CODE_2
	addis	r6, 0, 0x1000
	ori	r6, r6, 0x0001
	stb	r7,0(r6)
	eieio
fmerr:	bl	fmerr

fmfound:addi	r6, 0, 1
	subf	r3, r6, r3

	mtlr    r5                     /* restore lr */
	blr

/*--------------------------------------------------------------------- */
/* Function:    find_size_code */
/* Description: Determines size code to be used in configuring SDRAM controller */
/*		dependent on density (r15 = byte 31 from SPD) */
/*--------------------------------------------------------------------- */
find_size_code:

	mflr	r5

	addi	r3, r15, 0	/* density */
	addi	r7, 0, 0
fs01:	andi.	r6, r3, 0x01
	cmpi	0, r6, 1
	beq	fs04

	addi	r7, r7, 1
	cmpi	0, r7, 7
	bge	fs02
	addi	r9, 0, 1
	srw	r3, r3, r9
	bl	fs01

	/* not found, error code to be issued on LEDs */
fs02:	addi	r4, 0, LED_SDRAM_CODE_3
	addis	r8, 0, 0x1000
	ori	r8, r8, 0x0001
	stb	r4,0(r8)
	eieio
fs03:	bl	fs03

fs04:	addi	r3, r7, 0
	cmpi	0, r3, 0
	beq	fs05
	addi	r6, 0, 1
	subf	r3, r6, r3
fs05:
	mtlr    r5                     /* restore lr */
	blr

/*--------------------------------------------------------------------- */
/* Function:    find_casl */
/* Description: Determines CAS latency */
/*--------------------------------------------------------------------- */
find_casl:

	mflr	r5

	andi.	r14, r14, 0x7f	/* r14 holds supported CAS latencies */
	addi	r3, 0, 0xff	/* preset determined CASL */
	addi	r4, 0, 6	/* Start at bit 6 of supported CAS latencies */
	addi	r2, 0, 0	/* Start finding highest CAS latency */

fc01:	srw	r6, r14, r4	/*  */
	andi.	r6, r6, 0x01	/*  */
	cmpi	0, r6, 1	/* Check bit for current latency */
	bne	fc06		/* If not supported, go to next */

	cmpi	0, r2, 2	/* Check if third-highest latency */
	bge	fc04		/* If so, go calculate with another format */

	cmpi	0, r2, 0	/* Check if highest latency */
	bgt	fc02		/* */
	addi	r7, r19, 0	/* SDRAM cycle time for highest CAS latenty */

	bl	fc03
fc02:
	addi	r7, r20, 0	/* SDRAM cycle time for next-highest CAS latenty */
fc03:
	addi	r8, r7, 0
	addi	r9, 0, 4
	srw	r7, r7, r9
	andi.	r7, r7, 0x0f
	mulli	r7, r7, 100
	andi.	r8, r8, 0x0f
	mulli	r8, r8, 10
	add	r7, r7, r8
	cmp	0, r7, r30
	bgt	fc05
	addi	r3, r2, 0
	bl	fc05
fc04:
	addi	r7, r21, 0	/* SDRAM cycle time for third-highest CAS latenty */
	addi	r8, r7, 0
	addi	r9, 0, 2
	srw	r7, r7, r9
	andi.	r7, r7, 0x3f
	mulli	r7, r7, 100
	andi.	r8, r8, 0x03
	mulli	r8, r8, 25
	add	r7, r7, r8

	cmp	0, r7, r30
	bgt	fc05
	addi	r3, r2, 0

fc05:	addi	r2, r2, 1	/* next latency */
	cmpi	0, r2, 3
	bge	fc07
fc06:	addi	r6, 0, 1
	subf	r4, r6, r4
	cmpi	0, r4, 0
	bne	fc01

fc07:

	mtlr    r5		/* restore lr */
	blr
#endif


/*  Peripheral Bank 1 Access Parameters */
/*     0	BME = 1	; burstmode enabled */
/*    " 1:8"	TWT=00110110	;Transfer wait (details below) */
/*     1:5	FWT=00110	; first wait = 6 cycles */
/*     6:8	BWT=110	; burst wait = 6 cycles */
/*     9:11	000	; reserved */
/*     12:13	CSN=00	; chip select on timing = 0 */
/*     14:15	OEN=01	; output enable  */
/*     16:17	WBN=01	; write byte enable on timing 1 cycle */
/*     18:19	WBF=01	; write byte enable off timing 1 cycle */
/*     20:22	TH=010	; transfer hold = 2 cycles */
/*     23	RE=0	; ready enable = disabled */
/*     24	SOR=1	; sample on ready = same PerClk */
/*     25	BEM=0	; byte enable mode = only for write cycles */
/*     26	PEN=0	; parity enable = disable */
/*     27:31	00000	;reserved */
/* */
/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
/* */
/* */
/*	Code for BDI probe: */
/* */
/* WDCR    18      0x00000011      ;Select PB1AP */
/* WDCR    19      0x1b015480      ;PB1AP: Flash */
/* */
/* Peripheral Bank 0 Access Parameters */
/* 0:11	BAS=0x200	; base address select = 0x200 * 0x100000 (1MB) =  */
/* 12:14	BS=100	; bank size =  16MB (100) / 32MB (101) */
/* 15:16	BU=11	; bank usage = read/write */
/* 17:18	BW=00	; bus width = 8-bit */
/* 19:31		; reserved */
/* */
/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
/* WDCR    18      0x00000001      ;Select PB1CR */
/* WDCR    19      0x20098000      ;PB1CR: 1MB at 0x00100000, r/w, 8bit */

/* For CPLD */
/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
/*	WDCR_EBC(pb5ap, 0x01010040) */
/*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
/*	WDCR_EBC(pb5cr, 0X10018000) */
/* Access parms */
/*   100   3      8          0    0    0 */
/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
/* Address :	0x10000000 */
/* Size:	2 MB */
/* Usage:	read/write */
/* Width:	32 bit */

/* For Genie onboard fpga 32 bit interface */
/* 0      1      0         1         0         0         0            0 */
/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
/* 0x01010000 */
/* Access parms */
/*   102   1      c          0    0    0 */
/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
/* Address :	0x10200000 */
/* Size:	2 MB */
/* Usage:	read/write */
/* Width:	32 bit */

/* Walnut fpga pb7ap */
/* 0      1      8         1         5         2         8            0 */
/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
/* Walnut fpga pb7cr */
/* 0xF0318000 */
/*  */