init.s

UBOOT 源码

/*----------------------------------------------------------------------+
 *
 *       This source code has been made available to you by IBM on an AS-IS
 *       basis.  Anyone receiving this source is licensed under IBM
 *       copyrights to use it in any way he or she deems fit, including
 *       copying it, modifying it, compiling it, and redistributing it either
 *       with or without modifications.  No license under IBM patents or
 *       patent applications is to be implied by the copyright license.
 *
 *       Any user of this software should understand that IBM cannot provide
 *       technical support for this software and will not be responsible for
 *       any consequences resulting from the use of this software.
 *
 *       Any person who transfers this source code or any derivative work
 *       must include the IBM copyright notice, this paragraph, and the
 *       preceding two paragraphs in the transferred software.
 *
 *       COPYRIGHT   I B M   CORPORATION 1995
 *       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *-----------------------------------------------------------------------
 */

#include <config.h>
#include <ppc4xx.h>
#include "config.h"

#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
#define FPGA_BRDC       0xF0300004

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#include "exbitgen.h"

/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
/* c-code declarations and consequently can't be included here). */
/* (Possibly to be solved somehow else). */
/*--------------------------------------------------------------------- */
#define	   I2C_REGISTERS_BASE_ADDRESS 0xEF600500
#define    IIC_MDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
#define    IIC_SDBUF	(I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
#define    IIC_LMADR	(I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
#define    IIC_HMADR	(I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
#define    IIC_CNTL	(I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
#define    IIC_MDCNTL	(I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
#define    IIC_STS	(I2C_REGISTERS_BASE_ADDRESS+IICSTS)
#define    IIC_EXTSTS	(I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
#define    IIC_LSADR	(I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
#define    IIC_HSADR	(I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
#define    IIC_CLKDIV	(I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
#define    IIC_INTRMSK	(I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
#define    IIC_XFRCNT	(I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
#define    IIC_XTCNTLSS	(I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
#define    IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)

/* MDCNTL Register Bit definition */
#define    IIC_MDCNTL_HSCL 0x01
#define    IIC_MDCNTL_EUBS 0x02
#define    IIC_MDCNTL_FMDB 0x40
#define    IIC_MDCNTL_FSDB 0x80

/* CNTL Register Bit definition */
#define    IIC_CNTL_PT     0x01
#define    IIC_CNTL_READ   0x02
#define    IIC_CNTL_CHT    0x04

/* STS Register Bit definition */
#define    IIC_STS_PT	   0X01
#define    IIC_STS_ERR	   0X04
#define    IIC_STS_MDBS    0X20

/* EXTSTS Register Bit definition */
#define    IIC_EXTSTS_XFRA 0X01
#define    IIC_EXTSTS_ICT  0X02
#define    IIC_EXTSTS_LA   0X04

/* LED codes used for inditing progress and errors during read of DIMM SPD.  */
/*--------------------------------------------------------------------- */
#define LED_SDRAM_CODE_1  0xef
#define LED_SDRAM_CODE_2  0xee
#define LED_SDRAM_CODE_3  0xed
#define LED_SDRAM_CODE_4  0xec
#define LED_SDRAM_CODE_5  0xeb
#define LED_SDRAM_CODE_6  0xea
#define LED_SDRAM_CODE_7  0xe9
#define LED_SDRAM_CODE_8  0xe8
#define LED_SDRAM_CODE_9  0xe7
#define LED_SDRAM_CODE_10 0xe6
#define LED_SDRAM_CODE_11 0xe5
#define LED_SDRAM_CODE_12 0xe4
#define LED_SDRAM_CODE_13 0xe3
#define LED_SDRAM_CODE_14 0xe2
#define LED_SDRAM_CODE_15 0xe1
#define LED_SDRAM_CODE_16 0xe0


#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100

#define FLASH_8bit_AP   0x9B015480
#define FLASH_8bit_CR   0xFFF18000 /* 1MB(min), 8bit, R/W */

#define FLASH_32bit_AP  0x9B015480
#define FLASH_32bit_CR  0xFFE3C000 /* 2MB, 32bit, R/W */


#define WDCR_EBC(reg,val) addi    r4,0,reg;\
	mtdcr   ebccfga,r4;\
	addis   r4,0,val@h;\
	ori     r4,r4,val@l;\
	mtdcr   ebccfgd,r4

/*---------------------------------------------------------------------
 * Function:     ext_bus_cntlr_init
 * Description:  Initializes the External Bus Controller for the external
 *		peripherals. IMPORTANT: For pass1 this code must run from
 *		cache since you can not reliably change a peripheral banks
 *		timing register (pbxap) while running code from that bank.
 *		For ex., since we are running from ROM on bank 0, we can NOT
 *		execute the code that modifies bank 0 timings from ROM, so
 *		we run it from cache.
 *	Bank 0 - Boot flash
 *	Bank 1-4 - application flash
 *	Bank 5 - CPLD
 *	Bank 6 - not used
 *	Bank 7 - Heathrow chip
 *---------------------------------------------------------------------
 */
	.globl	ext_bus_cntlr_init
ext_bus_cntlr_init:
	mflr    r4                      /* save link register */
	bl      ..getAddr
..getAddr:
	mflr    r3                      /* get address of ..getAddr */
	mtlr    r4                      /* restore link register */
	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
	mtctr   r4                      /* 10 cache lines to fit this function */
					/* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
	addi    r3,r3,32		/* move to next cache line */
	bdnz    ..ebcloop               /* continue for 10 cache lines */

	mflr	r31			/* save link register */

	/*-----------------------------------------------------------
	 * Delay to ensure all accesses to ROM are complete before changing
	 * bank 0 timings. 200usec should be enough.
	 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
	 *-----------------------------------------------------------
	 */

	addis	r3,0,0x0
	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
	mtctr   r3
..spinlp:
	bdnz    ..spinlp                /* spin loop */

	/*---------------------------------------------------------------
	 * Memory Bank 0 (Boot Flash) initialization
	 *---------------------------------------------------------------
	 */
	WDCR_EBC(pb0ap, FLASH_32bit_AP)
	WDCR_EBC(pb0cr, 0xffe38000)
/*pnc	WDCR_EBC(pb0cr, FLASH_32bit_CR) */

	/*---------------------------------------------------------------
	 * Memory Bank 5 (CPLD) initialization
	 *---------------------------------------------------------------
	 */
	WDCR_EBC(pb5ap, 0x01010040)
/*jsa recommendation:		WDCR_EBC(pb5ap, 0x00010040) */
	WDCR_EBC(pb5cr, 0x10038000)

	/*--------------------------------------------------------------- */
	/* Memory Bank 6 (not used) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb6cr, 0x00000000)

	/* Read HW ID to determine whether old H2 board or new generic CPU board */
	addis	r3, 0,  HW_ID_ADDR@h
	ori	r3, r3, HW_ID_ADDR@l
	lbz     r3,0x0000(r3)
	cmpi	0, r3, 1          /* if (HW_ID==1) */
	beq 	setup_h2evalboard /* then jump */
	cmpi	0, r3, 2          /* if (HW_ID==2) */
	beq 	setup_genieboard  /* then jump */
	cmpi	0, r3, 3          /* if (HW_ID==3) */
	beq 	setup_genieboard  /* then jump */

setup_genieboard:
	/*--------------------------------------------------------------- */
	/* Memory Bank 1 (Application Flash) initialization for generic CPU board */
	/*--------------------------------------------------------------- */
/*	WDCR_EBC(pb1ap, 0x7b015480)	/###* T.B.M. */
/*	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
	WDCR_EBC(pb1ap, 0x9b015480)	/* hlb-20020207: burst 8 bit 6 cycles  */

/*	WDCR_EBC(pb1cr, 0x20098000)	/###* 16 MB */
	WDCR_EBC(pb1cr, 0x200B8000)	/* 32 MB */

	/*--------------------------------------------------------------- */
	/* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb4ap, 0x01010000)	/*  */
	WDCR_EBC(pb4cr, 0x1021c000)	/*  */

	/*--------------------------------------------------------------- */
	/* Memory Bank 7 (Heathrow chip on Reference board) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb7ap, 0x200ffe80)	/* No Ready, many wait states (let reflections die out) */
	WDCR_EBC(pb7cr, 0X4001A000)

	bl	setup_continue


setup_h2evalboard:
	/*--------------------------------------------------------------- */
	/* Memory Bank 1 (Application Flash) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb1ap, 0x7b015480)	/* T.B.M. */
/*3010	WDCR_EBC(pb1ap, 0x7F8FFE80)	/###* T.B.M. */
	WDCR_EBC(pb1cr, 0x20058000)

	/*--------------------------------------------------------------- */
	/* Memory Bank 2 (Application Flash) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb2ap, 0x7b015480)	/* T.B.M. */
/*3010	WDCR_EBC(pb2ap, 0x7F8FFE80)	/###* T.B.M. */
	WDCR_EBC(pb2cr, 0x20458000)

	/*--------------------------------------------------------------- */
	/* Memory Bank 3 (Application Flash) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb3ap, 0x7b015480)	/* T.B.M. */
/*3010	WDCR_EBC(pb3ap, 0x7F8FFE80)	/###* T.B.M. */
	WDCR_EBC(pb3cr, 0x20858000)

	/*--------------------------------------------------------------- */
	/* Memory Bank 4 (Application Flash) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb4ap, 0x7b015480)	/* T.B.M. */
/*3010	WDCR_EBC(pb4ap, 0x7F8FFE80)	/###* T.B.M. */
	WDCR_EBC(pb4cr, 0x20C58000)

	/*--------------------------------------------------------------- */
	/* Memory Bank 7 (Heathrow chip) initialization */
	/*--------------------------------------------------------------- */
	WDCR_EBC(pb7ap, 0x02000280)	/* No Ready, 4 wait states */
	WDCR_EBC(pb7cr, 0X4001A000)

setup_continue:


	mtlr    r31                     /* restore lr	 */
	nop				/* pass2 DCR errata #8 */
	blr

/*--------------------------------------------------------------------- */
/* Function:     sdram_init */
/* Description:  Configures SDRAM memory banks. */
/*--------------------------------------------------------------------- */
	.globl  sdram_init

sdram_init:
#if CFG_MONITOR_BASE < CFG_FLASH_BASE
	blr
#else
	mflr	r31

	/* output SDRAM code  on LEDs */
	addi	r4, 0, LED_SDRAM_CODE_1
	addis	r5, 0, 0x1000
	ori	r5, r5, 0x0001
	stb	r4,0(r5)
	eieio

	/* Read contents of spd */
	/*--------------------- */
	bl	read_spd

	/*----------------------------------------------------------- */
	/* */
	/* */
	/* Update SDRAM timing register */
	/* */
	/* */
	/*----------------------------------------------------------- */

	/* Read  PLL feedback divider and calculate clock period of local bus in */
	/* granularity of 10 ps. Save clock period in r30 */
	/*-------------------------------------------------------------- */
	mfdcr	r4, pllmd
	addi	r9, 0, 25
	srw	r4, r4, r9
	andi.	r4, r4, 0x07
	addis	r5, 0,  TIMEBASE_10PS@h
	ori	r5, r5, TIMEBASE_10PS@l
	divwu	r30, r5, r4

	/* Determine CASL */
	/*--------------- */
	bl	find_casl	/* Returns CASL in r3 */

	/* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
	/* (trp read from byte 27 in granularity of 1 ns) */
	/*------------------------------------------------ */
	mulli	r16, r16, 100
	add	r16, r16, r30
	addi	r6, 0, 1
	subf	r16, r6, r16
	divwu	r16, r16, r30

	/* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
	/* (trcd read from byte 29 in granularity of 1 ns) */
	/*--------------------------------------------------- */
	mulli	r17, r17, 100
	add	r17, r17, r30
	addi	r6, 0, 1
	subf	r17, r6, r17
	divwu	r17, r17, r30

	/* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
	/* (tras read from byte 30 in granularity of 1 ns) */
	/*--------------------------------------------------- */
	mulli	r18, r18, 100
	add	r18, r18, r30
	addi	r6, 0, 1
	subf	r18, r6, r18
	divwu	r18, r18, r30

	/* Calc trc_clocks = trp_clocks + tras_clocks */
	/*------------------------------------------- */
	add	r18, r18, r16

	/* CASL value */
	/*----------- */
	addi	r9, 0, 23
	slw	r4, r3, r9

	/* PTA = trp_clocks - 1 */
	/*--------------------- */
	addi	r6, 0, 1
	subf	r5, r6, r16
	addi	r9, 0, 18
	slw	r5, r5, r9
	or	r4, r4, r5

	/* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
	/*------------------------------------------------ */
	addi	r5, r18, 0
	subf	r5, r16, r5
	subf	r5, r17, r5
	addi	r6, 0, 1
	subf	r5, r6, r5
	addi	r9, 0, 16
	slw	r5, r5, r9
	or	r4, r4, r5

	/* LDF = 1 */
	/*-------- */
	ori	r4, r4, 0x4000

	/* RFTA = trc_clocks - 4 */
	/*---------------------- */
	addi	r6, 0, 4
	subf	r5, r6, r18
	addi	r9, 0, 2
	slw	r5, r5, r9
	or	r4, r4, r5

	/* RCD = trcd_clocks - 1 */
	/*---------------------- */
	addi	r6, 0, 1
	subf	r5, r6, r17
	or	r4, r4, r5

	/*----------------------------------------------------------- */
	/* Set SDTR1  */
	/*----------------------------------------------------------- */
	addi    r5,0,mem_sdtr1
	mtdcr   memcfga,r5
	mtdcr   memcfgd,r4

	/*----------------------------------------------------------- */
	/* */
	/* */
	/* Update memory bank 0-3 configuration registers */
	/* */
	/* */
	/*----------------------------------------------------------- */

	/* Build contents of configuration register for bank 0 into r6 */
	/*------------------------------------------------------------ */
	bl	find_mode	/* returns addressing mode in r3 */
	addi	r29, r3, 0	/* save mode temporarily in r29 */
	bl	find_size_code	/* returns size code in r3 */
	addi	r9, 0, 17	/* bit offset of size code in configuration register */
	slw	r3, r3, r9	/* */
	addi	r9, 0, 13	/* bit offset of addressing mode in configuration register  */
	slw	r29, r29, r9	/*  */
	or	r3, r29, r3	/* merge size code and addressing mode */
	ori	r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */

	/* Calculate banksize r15 = (density << 22) / 2 */
	/*--------------------------------------------- */
	addi	r9, 0, 21
	slw	r15, r15, r9

	/* Set SDRAM bank 0 register and adjust r6 for next bank */
	/*------------------------------------------------------ */
	addi    r7,0,mem_mb0cf
	mtdcr   memcfga,r7
	mtdcr   memcfgd,r6

	add	r6, r6, r15	/* add bank size to base address for next bank */

	/* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
	/*---------------------------------------------------------------------------- */
	cmpi	0, r12, 2
	bne	b1skip

	addi    r7,0,mem_mb1cf
	mtdcr   memcfga,r7
	mtdcr   memcfgd,r6

	add	r6, r6, r15	/* add bank size to base address for next bank */

	/* Set SDRAM bank 2 register and adjust r6 for next bank */
	/*------------------------------------------------------ */
b1skip:	addi    r7,0,mem_mb2cf
	mtdcr   memcfga,r7
	mtdcr   memcfgd,r6

	add	r6, r6, r15	/* add bank size to base address for next bank */

	/* If two rows/banks then set SDRAM bank 3 register */
	/*------------------------------------------------ */
	cmpi	0, r12, 2
	bne	b3skip

	addi    r7,0,mem_mb3cf
	mtdcr   memcfga,r7
	mtdcr   memcfgd,r6
b3skip:

	/*----------------------------------------------------------- */
	/* Set RTR */
	/*----------------------------------------------------------- */
	cmpi	0, r30, 1600
	bge	rtr_1
	addis   r7, 0, 0x05F0	/* RTR value for 100Mhz */
	bl	rtr_2
rtr_1:	addis	r7, 0, 0x03F8
rtr_2:	addi    r4,0,mem_rtr
	mtdcr   memcfga,r4
	mtdcr   memcfgd,r7

	/*----------------------------------------------------------- */
	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
	/* case that the core is running 200Mhz: */
	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
	/*----------------------------------------------------------- */
	addis   r3,0,0x0000
	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
	mtctr   r3
..spinlp2:
	bdnz    ..spinlp2               /* spin loop */

	/*----------------------------------------------------------- */
	/* Set memory controller options reg, MCOPT1. */
	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst  */
	/* read/prefetch. */
	/*----------------------------------------------------------- */
	addi    r4,0,mem_mcopt1
	mtdcr   memcfga,r4
	addis   r4,0,0x80C0             /* set DC_EN=1 */
	ori     r4,r4,0x0000
	mtdcr   memcfgd,r4


	/*----------------------------------------------------------- */
	/* Delay to ensure 10msec have elapsed since reset. This is */
	/* required for the MPC952 to stabalize. Assume worst */
	/* case that the core is running 200Mhz: */
	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
	/* This delay should occur before accessing SDRAM. */
	/*----------------------------------------------------------- */
	addis   r3,0,0x001E
	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
	mtctr   r3
..spinlp3:
	bdnz    ..spinlp3                /* spin loop */

	/* output SDRAM code  on LEDs */
	addi	r4, 0, LED_SDRAM_CODE_16
	addis	r5, 0, 0x1000
	ori	r5, r5, 0x0001
	stb	r4,0(r5)
	eieio

	mtlr    r31                     /* restore lr */
	blr