ns7520_eth.h

UBOOT 源码

#define NS7520_ETH_MAC1_RXEN	 (0x00000001)	/* Receive enable */

/* MAC Configuration Register 2 Bit Fields*/

#define NS7520_ETH_MAC2_RES1 	 (0xFFFF8000)	/* Reserved */
#define NS7520_ETH_MAC2_EDEFER	 (0x00004000)	/* Excess Deferral */
#define NS7520_ETH_MAC2_BACKP	 (0x00002000)	/* Backpressure/NO back off */
#define NS7520_ETH_MAC2_NOBO	 (0x00001000)	/* No back off */
#define NS7520_ETH_MAC2_RES2	 (0x00000C00)	/* Reserved */
#define NS7520_ETH_MAC2_LONGP	 (0x00000200)	/* Long Preable enforcement */
#define NS7520_ETH_MAC2_PUREP	 (0x00000100)	/* Pure preamble enforcement */
#define NS7520_ETH_MAC2_AUTOP	 (0x00000080)	/* Auto detect PAD enable */
#define NS7520_ETH_MAC2_VLANP	 (0x00000040)	/* VLAN pad enable */
#define NS7520_ETH_MAC2_PADEN  	 (0x00000020)	/* PAD/CRC enable */
#define NS7520_ETH_MAC2_CRCEN	 (0x00000010)	/* CRC enable */
#define NS7520_ETH_MAC2_DELCRC	 (0x00000008)	/* Delayed CRC */
#define NS7520_ETH_MAC2_HUGE	 (0x00000004)	/* Huge frame enable */
#define NS7520_ETH_MAC2_FLENC	 (0x00000002)	/* Frame length checking */
#define NS7520_ETH_MAC2_FULLD	 (0x00000001)	/* Full duplex */

/* IPGT Back-to-Back Inter-Packet-Gap Register Bit Fields*/

#define NS7520_ETH_IPGT_RES	 (0xFFFFFF80)	/* Reserved */
#define NS7520_ETH_IPGT_IPGT	 (0x0000007F)	/* Back-to-Back Interpacket Gap */

/* IPGR Non Back-to-Back Inter-Packet-Gap Register Bit Fields*/

#define NS7520_ETH_IPGR_RES1	 (0xFFFF8000)	/* Reserved */
#define NS7520_ETH_IPGR_IPGR1	 (0x00007F00)	/* Non Back-to-back Interpacket Gap */
#define NS7520_ETH_IPGR_RES2	 (0x00000080)	/* Reserved */
#define NS7520_ETH_IPGR_IPGR2	 (0x0000007F)	/* Non back-to-back Interpacket Gap */

/* CLRT Collision Windows/Collision Retry Register Bit Fields*/

#define NS7520_ETH_CLRT_RES1	 (0xFFFFC000)	/* Reserved */
#define NS7520_ETH_CLRT_CWIN	 (0x00003F00)	/* Collision Windows */
#define NS7520_ETH_CLRT_RES2	 (0x000000F0)	/* Reserved */
#define	NS7520_ETH_CLRT_RETX	 (0x0000000F)	/* Retransmission maximum */

/* MAXF Maximum Frame Register Bit Fields*/

#define NS7520_ETH_MAXF_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_MAXF_MAXF	 (0x0000FFFF)	/* Maximum frame length */

/* SUPP PHY Support Register Bit Fields*/

#define NS7520_ETH_SUPP_RES1	 (0xFFFFFF00)	/* Reserved */
#define NS7520_ETH_SUPP_RPE100X	 (0x00000080)	/* Reset PE100X module */
#define NS7520_ETH_SUPP_FORCEQ	 (0x00000040)	/* Force Quit */
#define NS7520_ETH_SUPP_NOCIPH	 (0x00000020)	/* No Cipher */
#define NS7520_ETH_SUPP_DLINKF	 (0x00000010)	/* Disable link fail */
#define NS7520_ETH_SUPP_RPE10T	 (0x00000008)	/* Reset PE10T module */
#define NS7520_ETH_SUPP_RES2	 (0x00000004)	/* Reserved */
#define NS7520_ETH_SUPP_JABBER	 (0x00000002)	/* Enable Jabber protection */
#define NS7520_ETH_SUPP_BITMODE	 (0x00000001)	/* Bit Mode */

/* TEST Register Bit Fields*/

#define NS7520_ETH_TEST_RES1	 (0xFFFFFFF8)	/* Reserved */
#define NS7520_ETH_TEST_TBACK	 (0x00000004)	/* Test backpressure */
#define NS7520_ETH_TEST_TPAUSE	 (0x00000002)	/* Test Pause */
#define NS7520_ETH_TEST_SPQ	 (0x00000001)	/* Shortcut pause quanta */

/* MCFG MII Management Configuration Register Bit Fields*/

#define NS7520_ETH_MCFG_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_MCFG_RMIIM	 (0x00008000)	/* Reset MII management */
#define NS7520_ETH_MCFG_RES2	 (0x00007FE0)	/* Reserved */
#define NS7520_ETH_MCFG_CLKS_MA	 (0x0000001C)	/* Clock Select */
#define NS7520_ETH_MCFG_CLKS_4	 (0x00000004)	/* Sysclk / 4 */
#define NS7520_ETH_MCFG_CLKS_6	 (0x00000008)	/* Sysclk / 6 */
#define NS7520_ETH_MCFG_CLKS_8	 (0x0000000C)	/* Sysclk / 8 */
#define NS7520_ETH_MCFG_CLKS_10	 (0x00000010)	/* Sysclk / 10 */
#define NS7520_ETH_MCFG_CLKS_14	 (0x00000014)	/* Sysclk / 14 */
#define NS7520_ETH_MCFG_CLKS_20	 (0x00000018)	/* Sysclk / 20 */
#define NS7520_ETH_MCFG_CLKS_28	 (0x0000001C)	/* Sysclk / 28 */
#define NS7520_ETH_MCFG_SPRE	 (0x00000002)	/* Suppress preamble */
#define NS7520_ETH_MCFG_SCANI	 (0x00000001)	/* Scan increment */

/* MCMD MII Management Command Register Bit Fields*/

#define NS7520_ETH_MCMD_RES1	 (0xFFFFFFFC)	/* Reserved */
#define NS7520_ETH_MCMD_SCAN	 (0x00000002)	/* Automatically Scan for Read Data */
#define NS7520_ETH_MCMD_READ	 (0x00000001)	/* Single scan for Read Data */

/* MCMD MII Management Address Register Bit Fields*/

#define NS7520_ETH_MADR_RES1	 (0xFFFFE000)	/* Reserved */
#define NS7520_ETH_MADR_DADR	 (0x00001F00)	/* MII PHY device address */
#define NS7520_ETH_MADR_RES2	 (0x000000E0)	/* Reserved */
#define NS7520_ETH_MADR_RADR	 (0x0000001F)	/* MII PHY register address */

/* MWTD MII Management Write Data Register Bit Fields*/

#define NS7520_ETH_MWTD_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_MWTD_MWTD	 (0x0000FFFF)	/* MII Write Data */

/* MRRD MII Management Read Data Register Bit Fields*/

#define NS7520_ETH_MRRD_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_MRRD_MRDD	 (0x0000FFFF)	/* MII Read Data */

/* MIND MII Management Indicators Register Bit Fields*/

#define NS7520_ETH_MIND_RES1	 (0xFFFFFFF8)	/* Reserved */
#define NS7520_ETH_MIND_NVALID	 (0x00000004)	/* Read Data not valid */
#define NS7520_ETH_MIND_SCAN	 (0x00000002)	/* Automatically scan for read data */
#define NS7520_ETH_MIND_BUSY	 (0x00000001)	/* MII interface busy */

/* SMII Status Register Bit Fields*/

#define NS7520_ETH_SMII_RES1	 (0xFFFFFFE0)	/* Reserved */
#define NS7520_ETH_SMII_CLASH	 (0x00000010)	/* MAC-to-MAC with PHY */
#define NS7520_ETH_SMII_JABBER	 (0x00000008)	/* Jabber condition present */
#define NS7520_ETH_SMII_LINK	 (0x00000004)	/* Link OK */
#define NS7520_ETH_SMII_DUPLEX	 (0x00000002)	/* Full-duplex operation */
#define NS7520_ETH_SMII_SPEED	 (0x00000001)	/* 100 Mbps */

/* SA1 Station Address 1 Register Bit Fields*/

#define NS7520_ETH_SA1_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_SA1_OCTET1	 (0x0000FF00)	/* Station Address octet 1 */
#define NS7520_ETH_SA1_OCTET2	 (0x000000FF)	/* Station Address octet 2 */

/* SA2 Station Address 2 Register Bit Fields*/

#define NS7520_ETH_SA2_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_SA2_OCTET3	 (0x0000FF00)	/* Station Address octet 3 */
#define NS7520_ETH_SA2_OCTET4	 (0x000000FF)	/* Station Address octet 4 */

/* SA3 Station Address 3 Register Bit Fields*/

#define NS7520_ETH_SA3_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_SA3_OCTET5	 (0x0000FF00)	/* Station Address octet 5 */
#define NS7520_ETH_SA3_OCTET6	 (0x000000FF)	/* Station Address octet 6 */

/* SAFR Station Address Filter Register Bit Fields*/

#define NS7520_ETH_SAFR_RES1	 (0xFFFFFFF0)	/* Reserved */
#define NS7520_ETH_SAFR_PRO	 (0x00000008)	/* Enable Promiscuous mode */
#define NS7520_ETH_SAFR_PRM	 (0x00000004)	/* Accept ALL multicast packets */
#define NS7520_ETH_SAFR_PRA	 (0x00000002)	/* Accept multicast packets table */
#define NS7520_ETH_SAFR_BROAD	 (0x00000001)	/* Accept ALL Broadcast packets */

/* HT1 Hash Table 1 Register Bit Fields*/

#define NS7520_ETH_HT1_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_HT1_HT1	 (0x0000FFFF)	/* CRC value 15-0 */

/* HT2 Hash Table 2 Register Bit Fields*/

#define NS7520_ETH_HT2_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_HT2_HT2	 (0x0000FFFF)	/* CRC value 31-16 */

/* HT3 Hash Table 3 Register Bit Fields*/

#define NS7520_ETH_HT3_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_HT3_HT3	 (0x0000FFFF)	/* CRC value 47-32 */

/* HT4 Hash Table 4 Register Bit Fields*/

#define NS7520_ETH_HT4_RES1	 (0xFFFF0000)	/* Reserved */
#define NS7520_ETH_HT4_HT4	 (0x0000FFFF)	/* CRC value 63-48 */

#endif				/* CONFIG_DRIVER_NS7520_ETHERNET */

#endif				/* FS_NS7520_ETH_H */