mpc824x.h

UBOOT 源码

#define ECCSBECR	0x800000b8  /* ECC Single-Bit Error Counter Register */
#define ECCSBETR	0x800000b8  /* ECC Single-Bit Error Trigger Register */
#define ERRENR1		0x800000c0  /* Error Enableing Register 1 */
#define ERRENR2		0x800000c4  /* Error Enableing Register 2 */
#define ERRDR1		0x800000c1  /* Error Detection Register 1 */
#define IPBESR		0x800000c3  /* Internal Processor Error Status Register */
#define ERRDR2		0x800000c5  /* Error Detection Register 2 */
#define PBESR		0x800000c7  /* PCI Bus Error Status Register */
#define PBEAR		0x800000c8  /* Processor/PCI Bus Error Status Register */
#define AMBOR		0x800000e0  /* Address Map B Options Register */
#define PCMBCR		0x800000e1  /* PCI/Memory Buffer Configuration */
#define MCCR1		0x800000f0  /* Memory Control Configuration Register 1 */
#define MCCR2		0x800000f4  /* Memory Control Configuration Register 2 */
#define MCCR3		0x800000f8  /* Memory Control Configuration Register 3 */
#define MCCR4		0x800000fc  /* Memory Control Configuration Register 4 */

/* some values for some of the above */

#define PICR1_CF_APARK		0x00000008
#define PICR1_LE_MODE		0x00000020
#define PICR1_ST_GATH_EN	0x00000040
#if defined(CONFIG_MPC8240)
#define PICR1_EN_PCS		0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define PICR1_NO_BUSW_CK	0x00000080 /* no bus width check for flash writes */
#define PICR1_DEC		0x00000100 /* Time Base enable on 8245/8241 */
#define ERCR1		        0x800000d0  /* Extended ROM Configuration Register 1 */
#define ERCR2		        0x800000d4  /* Extended ROM Configuration Register 2 */
#define ERCR3		        0x800000d8  /* Extended ROM Configuration Register 3 */
#define ERCR4		        0x800000dc  /* Extended ROM Configuration Register 4 */
#define MIOCR1		        0x80000076  /* Miscellaneous I/O Control Register 1 */
#define MIOCR1_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
#define MIOCR1_SHIFT	        2
#define MIOCR2		        0x80000077  /* Miscellaneous I/O Control Register 2 */
#define MIOCR2_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
#define MIOCR2_SHIFT	        3
#define ODCR_ADR_X	        0x80000070	/* Output Driver Control register */
#define ODCR_SHIFT              3
#define PMCR2_ADR	        0x80000072	/* Power Mgmnt Cfg 2 register */
#define PMCR2_ADR_X	        0x80000070
#define PMCR2_SHIFT             3
#define PMCR1_ADR	        0x80000070	/* Power Mgmnt Cfg 1 reister */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define PICR1_CF_DPARK		0x00000200
#define PICR1_MCP_EN		0x00000800
#define PICR1_FLASH_WR_EN	0x00001000
#ifdef CONFIG_MPC8240
#define PICR1_ADDRESS_MAP	0x00010000
#define PIRC1_MSK		0xff000000
#endif
#define PICR1_PROC_TYPE_MSK	0x00060000
#define PICR1_PROC_TYPE_603E	0x00040000
#define PICR1_RCS0		0x00100000

#define PICR2_CF_SNOOP_WS_MASK	0x000c0000
#define PICR2_CF_SNOOP_WS_0WS	0x00000000
#define PICR2_CF_SNOOP_WS_1WS	0x00040000
#define PICR2_CF_SNOOP_WS_2WS	0x00080000
#define PICR2_CF_SNOOP_WS_3WS	0x000c0000
#define PICR2_CF_APHASE_WS_MASK 0x0000000c
#define PICR2_CF_APHASE_WS_0WS	0x00000000
#define PICR2_CF_APHASE_WS_1WS	0x00000004
#define PICR2_CF_APHASE_WS_2WS	0x00000008
#define PICR2_CF_APHASE_WS_3WS	0x0000000c

#define MCCR1_ROMNAL_SHIFT	28
#define MCCR1_ROMNAL_MSK	0xf0000000
#define MCCR1_ROMFAL_SHIFT	23
#define MCCR1_ROMFAL_MSK	0x0f800000
#define MCCR1_DBUS_SIZE0        0x00400000
#define MCCR1_BURST		0x00100000
#define MCCR1_MEMGO		0x00080000
#define MCCR1_SREN		0x00040000
#if defined(CONFIG_MPC8240)
#define MCCR1_RAM_TYPE		0x00020000
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR1_SDRAM_EN		0x00020000
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR1_PCKEN		0x00010000
#define MCCR1_BANK1ROW_SHIFT	2
#define MCCR1_BANK2ROW_SHIFT	4
#define MCCR1_BANK3ROW_SHIFT	6
#define MCCR1_BANK4ROW_SHIFT	8
#define MCCR1_BANK5ROW_SHIFT	10
#define MCCR1_BANK6ROW_SHIFT	12
#define MCCR1_BANK7ROW_SHIFT	14

#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
#define MCCR2_TS_WAIT_TIMER_SHIFT 29
#define MCCR2_ASRISE_MSK	0x1e000000
#define MCCR2_ASRISE_SHIFT	25
#define MCCR2_ASFALL_MSK	0x01e00000
#define MCCR2_ASFALL_SHIFT	21

#define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
#define MCCR2_WRITE_PARITY_CHK	0x00080000
#define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
#ifdef CONFIG_MPC8240
#define MCCR2_ECC_EN		0x00020000
#define MCCR2_EDO		0x00010000
#endif
#define MCCR2_REFINT_MSK	0x0000fffc
#define MCCR2_REFINT_SHIFT	2
#define MCCR2_RSV_PG		0x00000002
#define MCCR2_PMW_PAR		0x00000001

#define MCCR3_BSTOPRE2TO5_MSK	0xf0000000 /*BSTOPRE[2-5]*/
#define MCCR3_BSTOPRE2TO5_SHIFT 28
#define MCCR3_REFREC_MSK	0x0f000000
#define MCCR3_REFREC_SHIFT	24
#ifdef CONFIG_MPC8240
#define MCCR3_RDLAT_MSK		0x00f00000
#define MCCR3_RDLAT_SHIFT	20
#define MCCR3_CPX		0x00010000
#define MCCR3_RAS6P_MSK		0x00078000
#define MCCR3_RAS6P_SHIFT	15
#define MCCR3_CAS5_MSK		0x00007000
#define MCCR3_CAS5_SHIFT	12
#define MCCR3_CP4_MSK		0x00000e00
#define MCCR3_CP4_SHIFT		9
#define MCCR3_CAS3_MSK		0x000001c0
#define MCCR3_CAS3_SHIFT	6
#define MCCR3_RCD2_MSK		0x00000038
#define MCCR3_RCD2_SHIFT	3
#define MCCR3_RP1_MSK		0x00000007
#define MCCR3_RP1_SHIFT		0
#endif

#define MCCR4_PRETOACT_MSK	0xf0000000
#define MCCR4_PRETOACT_SHIFT	28
#define MCCR4_ACTTOPRE_MSK	0x0f000000
#define MCCR4_ACTTOPRE_SHIFT	24
#define MCCR4_WMODE		0x00800000
#define MCCR4_INLINE		0x00400000
#if defined(CONFIG_MPC8240)
#define MCCR4_BIT21		0x00200000 /* this include cos DINK code sets it- unknown function*/
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR4_EXTROM		0x00200000 /* enables Extended ROM space */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR4_REGISTERED	0x00100000
#define MCCR4_BSTOPRE0TO1_MSK	0x000c0000 /*BSTOPRE[0-1]*/
#define MCCR4_BSTOPRE0TO1_SHIFT 18
#define MCCR4_REGDIMM		0x00008000
#define MCCR4_SDMODE_MSK	0x00007f00
#define MCCR4_SDMODE_SHIFT	8
#define MCCR4_ACTTORW_MSK	0x000000f0
#define MCCR4_ACTTORW_SHIFT	4
#define MCCR4_BSTOPRE6TO9_MSK	0x0000000f /*BSTOPRE[6-9]*/
#define MCCR4_BSTOPRE6TO9_SHIFT 0
#define MCCR4_DBUS_SIZE2_SHIFT	17

#define MICR_ADDR_MASK		0x0ff00000
#define MICR_ADDR_SHIFT		20
#define MICR_EADDR_MASK		0x30000000
#define MICR_EADDR_SHIFT	28

#define BATU_BEPI_MSK		0xfffe0000
#define BATU_BL_MSK		0x00001ffc

#define BATU_BL_128K		0x00000000
#define BATU_BL_256K		0x00000004
#define BATU_BL_512K		0x0000000c
#define BATU_BL_1M		0x0000001c
#define BATU_BL_2M		0x0000003c
#define BATU_BL_4M		0x0000007c
#define BATU_BL_8M		0x000000fc
#define BATU_BL_16M		0x000001fc
#define BATU_BL_32M		0x000003fc
#define BATU_BL_64M		0x000007fc
#define BATU_BL_128M		0x00000ffc
#define BATU_BL_256M		0x00001ffc

#define BATU_VS			0x00000002
#define BATU_VP			0x00000001

#define BATL_BRPN_MSK		0xfffe0000
#define BATL_WIMG_MSK		0x00000078

#define BATL_WRITETHROUGH	0x00000040
#define BATL_CACHEINHIBIT	0x00000020
#define BATL_MEMCOHERENCE	0x00000010
#define BATL_GUARDEDSTORAGE	0x00000008

#define BATL_PP_MSK		0x00000003
#define BATL_PP_00		0x00000000 /* No access */
#define BATL_PP_01		0x00000001 /* Read-only */
#define BATL_PP_10		0x00000002 /* Read-write */
#define BATL_PP_11		0x00000003

/*
 * I'd attempt to do defines for the PP bits, but it's use is a bit
 * too complex, see the PowerPC Operating Environment Architecture
 * section in the PowerPc arch book, chapter 4.
 */

/*eumb and epic config*/

#define EPIC_FPR		0x00041000
#define EPIC_GCR		0x00041020
#define EPIC_EICR		0x00041030
#define EPIC_EVI		0x00041080
#define EPIC_PI			0x00041090
#define EPIC_SVR		0x000410E0
#define EPIC_TFRR		0x000410F0

/*
 * Note the information for these is rather mangled in the 8240 manual.
 * These are guesses.
 */

#define EPIC_GTCCR0		0x00041100
#define EPIC_GTCCR1		0x00041140
#define EPIC_GTCCR2		0x00041180
#define EPIC_GTCCR3		0x000411C0
#define EPIC_GTBCR0		0x00041110
#define EPIC_GTBCR1		0x00041150
#define EPIC_GTBCR2		0x00041190
#define EPIC_GTBCR3		0x000411D0
#define EPIC_GTVPR0		0x00041120
#define EPIC_GTVPR1		0x00041160
#define EPIC_GTVPR2		0x000411a0
#define EPIC_GTVPR3		0x000411e0
#define EPIC_GTDR0		0x00041130
#define EPIC_GTDR1		0x00041170
#define EPIC_GTDR2		0x000411b0
#define EPIC_GTDR3		0x000411f0

#define EPIC_IVPR0		0x00050200
#define EPIC_IVPR1		0x00050220
#define EPIC_IVPR2		0x00050240
#define EPIC_IVPR3		0x00050260
#define EPIC_IVPR4		0x00050280

#define EPIC_SVPR0		0x00050200
#define EPIC_SVPR1		0x00050220
#define EPIC_SVPR2		0x00050240
#define EPIC_SVPR3		0x00050260
#define EPIC_SVPR4		0x00050280
#define EPIC_SVPR5		0x000502A0
#define EPIC_SVPR6		0x000502C0
#define EPIC_SVPR7		0x000502E0
#define EPIC_SVPR8		0x00050300
#define EPIC_SVPR9		0x00050320
#define EPIC_SVPRa		0x00050340
#define EPIC_SVPRb		0x00050360
#define EPIC_SVPRc		0x00050380
#define EPIC_SVPRd		0x000503A0
#define EPIC_SVPRe		0x000503C0
#define EPIC_SVPRf		0x000503E0

/* MPC8240 Byte Swap/PCI Support Macros */
#define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
		     (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
#define PCISWAP(x)   LONGSWAP(x)

#ifndef __ASSEMBLY__

/*
 * MPC107 Support
 *
 */
unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
unsigned char mpc824x_mpc107_read8(unsigned int address);
unsigned short mpc824x_mpc107_read16(unsigned int address);
unsigned int mpc824x_mpc107_read32(unsigned int address);
unsigned int mpc824x_eummbar_read(unsigned int regNum);
void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);

#ifdef CONFIG_PCI
struct pci_controller;
void pci_cpm824x_init(struct pci_controller* hose);
#endif

#endif /* __ASSEMBLY__ */

#endif /* __MPC824X_H__ */