📄 fi_diagcas2.mdl
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BlockType Outport
Name "Out1"
Position [245, 173, 275, 187]
Port "2"
OutputWhenDisabled "held"
InitialOutput "0"
}
Line {
SrcBlock "In"
SrcPort 1
Points [-15, 0]
Branch {
DstBlock "Switch"
DstPort 3
}
Branch {
Points [-40, 0]
DstBlock "Switch1"
DstPort 1
}
}
Line {
SrcBlock "Condition"
SrcPort 1
Points [20, 0]
Branch {
Points [0, 80]
DstBlock "Switch1"
DstPort 2
}
Branch {
Points [0, -15]
DstBlock "Switch"
DstPort 2
}
}
Line {
SrcBlock "Constant1"
SrcPort 1
DstBlock "Switch1"
DstPort 3
}
Line {
SrcBlock "Constant2"
SrcPort 1
Points [25, 0]
DstBlock "Switch"
DstPort 1
}
Line {
SrcBlock "Switch"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "Switch1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Sum6"
Ports [2, 1, 0, 0, 0]
Position [240, 75, 260, 95]
IconShape "rectangular"
Inputs "++"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Name "Out1"
Position [285, 78, 315, 92]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "Mdelay = 0"
SrcPort 1
Points [15, 0]
DstBlock "Mdelay\n> 0"
DstPort 1
}
Line {
SrcBlock "Mdelay\n> 0"
SrcPort 1
Points [15, 0]
DstBlock "Sum6"
DstPort 1
}
Line {
SrcBlock "Mdelay = 0"
SrcPort 2
DstBlock "Sum6"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Mdelay = 0"
DstPort 1
}
Line {
SrcBlock "Sum6"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Sum7"
Ports [2, 1, 0, 0, 0]
Position [265, 60, 285, 80]
IconShape "rectangular"
Inputs "++"
SaturateOnIntegerOverflow on
}
Block {
BlockType TransferFcn
Name "Transfer Fcn1"
Position [70, 19, 155, 61]
Numerator "XnumMs{1,1}"
Denominator "XdenMs{1,1}"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn3"
Position [75, 85, 155, 125]
Numerator "XnumMs{1,2}"
Denominator "XdenMs{1,2}"
}
Block {
BlockType Outport
Name "Out1"
Position [300, 63, 330, 77]
Port "1"
OutputWhenDisabled "held"
InitialOutput "0"
}
Line {
SrcBlock "Transfer Fcn1"
SrcPort 1
DstBlock "Mdelay"
DstPort 1
}
Line {
SrcBlock "Transfer Fcn3"
SrcPort 1
DstBlock "Mdelay1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Transfer Fcn1"
DstPort 1
}
Branch {
Points [0, 35]
DstBlock "Transfer Fcn3"
DstPort 1
}
}
Line {
SrcBlock "Sum7"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Mdelay"
SrcPort 1
DstBlock "Sum7"
DstPort 1
}
Line {
SrcBlock "Mdelay1"
SrcPort 1
DstBlock "Sum7"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "Multi_tf Process1"
Ports [1, 1, 0, 0, 0]
Position [570, 99, 650, 141]
ShowPortLabels on
System {
Name "Multi_tf Process1"
Location [565, 652, 956, 870]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "In1"
Position [25, 68, 55, 82]
Port "1"
PortWidth "-1"
SampleTime "-1"
DataType "auto"
SignalType "auto"
Interpolate on
}
Block {
BlockType SubSystem
Name "Pdelay"
Ports [1, 1, 0, 0, 0]
Position [195, 27, 245, 63]
ShowPortLabels on
System {
Name "Pdelay"
Location [389, 668, 752, 811]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "In1"
Position [25, 73, 55, 87]
Port "1"
PortWidth "-1"
SampleTime "-1"
DataType "auto"
SignalType "auto"
Interpolate on
}
Block {
BlockType TransportDelay
Name "Mdelay\n> 0"
Position [165, 25, 205, 55]
DelayTime "Xpdeadx{1,1}"
InitialInput "0"
BufferSize "1024"
}
Block {
BlockType SubSystem
Name "Mdelay = 0"
Description "pass input signal through out1 if condi"
"tion is true."
Ports [1, 2, 0, 0, 0]
Position [80, 60, 130, 100]
ShowPortLabels on
System {
Name "Mdelay = 0"
Location [415, 227, 766, 465]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "In"
Position [235, 133, 265, 147]
Orientation "left"
Port "1"
PortWidth "-1"
SampleTime "-1"
DataType "auto"
SignalType "auto"
Interpolate on
}
Block {
BlockType Constant
Name "Condition"
Position [20, 85, 130, 115]
Value "Xpdeadx{1,1}<=3*eps"
}
Block {
BlockType Constant
Name "Constant1"
Position [115, 180, 145, 200]
Value "0"
}
Block {
BlockType Constant
Name "Constant2"
Position [155, 50, 185, 70]
Value "0"
}
Block {
BlockType Switch
Name "Switch"
Position [230, 70, 260, 100]
Threshold "1"
}
Block {
BlockType Switch
Name "Switch1"
Position [190, 165, 220, 195]
Threshold "1"
}
Block {
BlockType Outport
Name "Out2"
Position [285, 78, 315, 92]
Port "1"
OutputWhenDisabled "held"
InitialOutput "0"
}
Block {
BlockType Outport
Name "Out1"
Position [245, 173, 275, 187]
Port "2"
OutputWhenDisabled "held"
InitialOutput "0"
}
Line {
SrcBlock "In"
SrcPort 1
Points [-15, 0]
Branch {
DstBlock "Switch"
DstPort 3
}
Branch {
Points [-40, 0]
DstBlock "Switch1"
DstPort 1
}
}
Line {
SrcBlock "Condition"
SrcPort 1
Points [20, 0]
Branch {
Points [0, 80]
DstBlock "Switch1"
DstPort 2
}
Branch {
Points [0, -15]
DstBlock "Switch"
DstPort 2
}
}
Line {
SrcBlock "Constant1"
SrcPort 1
DstBlock "Switch1"
DstPort 3
}
Line {
SrcBlock "Constant2"
SrcPort 1
Points [25, 0]
DstBlock "Switch"
DstPort 1
}
Line {
SrcBlock "Switch"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "Switch1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Sum6"
Ports [2, 1, 0, 0, 0]
Position [240, 75, 260, 95]
IconShape "rectangular"
Inputs "++"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Name "Out1"
Position [285, 78, 315, 92]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Line {
SrcBlock "Mdelay = 0"
SrcPort 1
Points [15, 0]
DstBlock "Mdelay\n> 0"
DstPort 1
}
Line {
SrcBlock "Mdelay\n> 0"
SrcPort 1
Points [15, 0]
DstBlock "Sum6"
DstPort 1
}
Line {
SrcBlock "Mdelay = 0"
SrcPort 2
DstBlock "Sum6"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
DstBlock "Mdelay = 0"
DstPort 1
}
Line {
SrcBlock "Sum6"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Pdelay1"
Ports [1, 1, 0, 0, 0]
Position [195, 102, 245, 138]
ShowPortLabels on
System {
Name "Pdelay1"
Location [391, 670, 754, 813]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "In1"
Position [25, 73, 55, 87]
Port "1"
PortWidth "-1"
SampleTime "-1"
DataType "auto"
SignalType "auto"
Interpolate on
}
Block {
BlockType TransportDelay
Name "Mdelay\n> 0"
Position [165, 25, 205, 55]
DelayTime "Xpdeadx{1,2}"
InitialInput "0"
BufferSize "1024"
}
Block {
BlockType SubSystem
Name "Mdelay = 0"
Description "pass input signal through out1 if condi"
"tion is true."
Ports [1, 2, 0, 0, 0]
Position [80, 60, 130, 100]
ShowPortLabels on
System {
Name "Mdelay = 0"
Location [417, 229, 768, 467]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "In"
Position [235, 133, 265, 147]
Orientation "left"
Port "1"
PortWidth "-1"
SampleTime "-1"
DataType "auto"
SignalType "auto"
Interpolate on
}
Block {
BlockType Constant
Name "Condition"
Position [20, 85, 130, 115]
Value "Xpdeadx{1,2}<=3*eps"
}
Block {
BlockType Constant
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