📄 boot.s
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ResetHandler
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK
ldr r1,=0x07ffffff ;all interrupt disable
str r1,[r0]
;****************************************************
;* Set clock control registers *
;****************************************************
ldr r0,=LOCKTIME
ldr r1,=0xfff
str r1,[r0]
ldr r0,=PLLCON ;temporary setting of PLL
ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV) ;Fin=10MHz,Fout=60MHz
str r1,[r0]
ldr r0,=CLKCON
ldr r1,=0x7ff8 ;All unit block CLK enable
str r1,[r0]
;****************************************************
;* Port Initialization *
;****************************************************
; del by plum
; ldr r0,=PCONA
; ldr r1,=0x3ff
; str r1,[r0] ;config GPIOA as addr. bus
; ldr r0,=PCONB
; ldr r1,=0x7ff
; str r1,[r0] ;config GPIOB as mem controller interface
; ldr r0,=PCONC
; ldr r1,=0xaaaaaaaa
; str r1,[r0] ;config GPIOC as data bus high bits
;****************************************
;* change BDMACON reset value for BDMA *
;****************************************
ldr r0,=BDIDES0
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0]
ldr r0,=BDIDES1
ldr r1,=0x40000000 ;BDIDESn reset value should be 0x40000000
str r1,[r0]
;****************************************
;* CPU cache and system bus config *
;****************************************
;ldr r0,=SYSCFG
;ldr r1,=0x0
;str r1,[r0] ;disable write buffer & make all inner_mem SRAM(no cache)
;****************************************************
;* Set memory control registers *
;****************************************************
ldr r0,=SMRDATA
ldmia r0,{r1-r13}
ldr r0,=BWSCON ;memory controller
stmia r0,{r1-r13}
;****************************************************
;* Clear 7LED display *
;****************************************************
;del by plum
; ldr r0,=0x02000000
; ldr r1,=0x0
; str r1,[r0]
; ldr r0,=0x1d20040 ;GPOIOG
; ldr r1,=0xff55 ;
; str r1,[r0]
; ldr r0,=0x1d20044
; ldr r1,=0xff
; str r1,[r0]
;****************************************************
;* Initialize stacks *
;****************************************************
ldr sp, =SVCStack ;
bl InitStacks
;del by plum
; mrs r0,cpsr
; bic r0,r0,#MODEMASK
; orr r1,r0,#UNDEFMODE|NOINT
; msr cpsr_cxsf,r1 ;UndefMode
; ldr sp,=UndefStack
; orr r1,r0,#ABORTMODE|NOINT
; msr cpsr_cxsf,r1 ;AbortMode
; ldr sp,=AbortStack
; orr r1,r0,#IRQMODE|NOINT
; msr cpsr_cxsf,r1 ;IRQMode
; ldr sp,=IRQStack
; orr r1,r0,#FIQMODE|NOINT
; msr cpsr_cxsf,r1 ;FIQMode
; ldr sp,=FIQStack
; orr r1,r0,#SVCMODE|NOINT
; msr cpsr_cxsf,r1 ;SVCMode
; ldr sp,=SVCStack
;****************************************************
;* Setup interrupt handler *
;****************************************************
ldr r0,=HandleIRQ ;
ldr r1,=IsrIRQ ;
str r1,[r0]
;del by plum
; ldr r0,=HandleFIQ ;
; ldr r1,=IsrFIQ ;
; str r1,[r0]
;********************************************************
;* Copy and paste RW data/zero initialized data *
;********************************************************
LDR r0, =|Image$$RO$$Limit| ; pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different
BEQ %F1
0
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B0
1
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B2
BL main ; jump to C program
B .
;****************************************************
;* The function for initializing stack *
;****************************************************
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;USER mode is not initialized.
mov pc,lr ;The LR register may be not valid for the mode changes.
;****************************************************
;* The function for entering power down mode *
;****************************************************
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;self-refresh enable
str r1, [r0]
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop ; mov r0, r0
nop
nop
nop
nop
;enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;wait until enter SL_IDLE,STOP mode and until wake-up
ldr r0,=0x10
0 subs r0,r0,#1
bne %B0
;exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
LTORG
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
SMRDATA DATA
DCD 0x22222220 ;Bank0=OM[1:0], Bank1~Bank7=32bit
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
;"SDRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x17 ;SCLK power down mode, BANKSIZE 16MB/16MB
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
AREA RamData, DATA, READWRITE
^ (_ISR_STARTADDRESS-0x500) ;0x500 = 256*5 _ISR_STARTADDRESS = 0xdff_ff00
UserStack # 256 ;c1(c7)ffa00
SVCStack # 256 ;c1(c7)ffb00
UndefStack # 256 ;c1(c7)ffc00
AbortStack # 256 ;c1(c7)ffd00
IRQStack # 256 ;c1(c7)ffe00
FIQStack # 0 ;c1(c7)fff00
^ _ISR_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
HandleADC # 4
HandleRTC # 4
HandleUTXD1 # 4
HandleUTXD0 # 4
HandleSIO # 4
HandleIIC # 4
HandleURXD1 # 4
HandleURXD0 # 4
HandleTIMER5 # 4
HandleTIMER4 # 4
HandleTIMER3 # 4
HandleTIMER2 # 4
HandleTIMER1 # 4
HandleTIMER0 # 4
HandleUERR01 # 4
HandleWDT # 4
HandleBDMA1 # 4
HandleBDMA0 # 4
HandleZDMA1 # 4
HandleZDMA0 # 4
HandleTICK # 4
HandleEINT4567 # 4
HandleEINT3 # 4
HandleEINT2 # 4
HandleEINT1 # 4
HandleEINT0 # 4
END
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