boot.s

一个ADS下的ucos-II的移植代码,大家

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;;		initialization     		;;
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	GET option_boot.h
	GET memcfg.h
	
;interrupt controller
INTPND EQU 0x01e00004
INTMOD EQU 0x01e00008
INTMSK EQU 0x01e0000c
I_ISPR EQU 0x01e00020
I_CMST EQU 0x01e0001c
;I_PMST EQU 0x01e00014		;del by plum

;Watchdog timer
WTCON EQU 0x01d30000

;Clock Controller
PLLCON EQU 0x01d80000
CLKCON EQU 0x01d80004
LOCKTIME EQU 0x01d8000c

;Memory Controller
REFRESH EQU 0x01c80024

;BDMAhdog timer
BDIDES0 EQU 0x1f80008
BDIDES1 EQU 0x1f80028

;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0

;port config register
;PCONA	EQU 0x01d20000		;del by plum
;PCONB	EQU 0x01d20008		;del by plum
;PCONC	EQU 0x01d20010		;del by plum

;mem controller
BWSCON	EQU 0x01c80000		


	MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
	sub sp,sp,#4 		;decrement sp(to store jump address)
	stmfd sp!,{r0} 		;PUSH the work register to stack(lr does't push because it return to original address)
	ldr r0,=$HandleLabel	;load the address of HandleXXX to r0
	ldr r0,[r0] 		;load the contents(service routine start address) of HandleXXX
	str r0,[sp,#4] 		;store the contents(ISR) of HandleXXX to stack
	ldmfd sp!,{r0,pc} 	;POP the work register and pc(jump to ISR)
	MEND

;del by plum
;	MACRO
;$HandlerLabel VHANDLER $HandleLabel
;$HandlerLabel
;	sub sp,sp,#4
;	stmfd sp!,{r0}
;	ldr r0,=I_ISPR ;INTMSK work-around
;	ldr r0,[r0]
;	cmp r0,#0x0
;	beq %F0
;	ldr r0,=$HandleLabel
;	ldr r0,[r0]
;	str r0,[sp,#4]
;	ldmfd sp!,{r0,pc}
;0 	stmfd sp!,{r1}
;	ldr r0,=I_PMST
;	ldr r1,[r0]
;	str r1,[r0]
;	ldmfd sp!,{r0,r1}
;	add sp,sp,#4
;	subs pc,lr,#4
;	MEND
	
	IMPORT |Image$$RO$$Limit| 	; End of ROM code
	IMPORT |Image$$RW$$Base| 	; Base of RAM to initialise
	IMPORT |Image$$ZI$$Base| 	; Base and limit of area
	IMPORT |Image$$ZI$$Limit| 	; to zero initialise
	
	IMPORT main 			; The main entry of mon program

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;;		coding area
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	AREA boot,CODE,READONLY
	ENTRY

	b ResetHandler ;for debug
	b HandlerUndef ;handlerUndef
	b HandlerSWI ;SWI interrupt handler
	b HandlerPabort ;handlerPAbort
	b HandlerDabort ;handlerDAbort
	b . ;handlerReserved
	b HandlerIRQ
	b HandlerFIQ
	;*** IMPORTANT NOTE ***
	;If the H/W vectored interrutp mode is enabled, The above two instruction should
	;be changed like below, to work-around with H/W bug of S3C44B0X interrupt controller.
	;If INTCON I,F bit is changed, this case may be occurred.
	; b HandlerIRQ -> subs pc,lr,#4
	; b HandlerIRQ -> subs pc,lr,#4
VECTOR_BRANCH
	ldr pc,=HandlerEINT0 ;mGA H/W interrupt vector table
	ldr pc,=HandlerEINT1 ;
	ldr pc,=HandlerEINT2 ;
	ldr pc,=HandlerEINT3 ;
	ldr pc,=HandlerEINT4567 ;
	ldr pc,=HandlerTICK ;mGA
	
	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef

	
	ldr pc,=HandlerZDMA0 ;mGB
	ldr pc,=HandlerZDMA1 ;
	ldr pc,=HandlerBDMA0 ;
	ldr pc,=HandlerBDMA1 ;
	ldr pc,=HandlerWDT ;
	ldr pc,=HandlerUERR01 ;mGB

	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
	
	ldr pc,=HandlerTIMER0 ;mGC
	ldr pc,=HandlerTIMER1 ;
	ldr pc,=HandlerTIMER2 ;
	ldr pc,=HandlerTIMER3 ;
	ldr pc,=HandlerTIMER4 ;
	ldr pc,=HandlerTIMER5 ;mGC

	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
	
	ldr pc,=HandlerURXD0 ;mGD
	ldr pc,=HandlerURXD1 ;
	ldr pc,=HandlerIIC ;
	ldr pc,=HandlerSIO ;
	ldr pc,=HandlerUTXD0 ;
	ldr pc,=HandlerUTXD1 ;mGD

	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
	
	ldr pc,=HandlerRTC ;mGKA

	b .
	b .
	b .
	b .
	b .
	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
 
	ldr pc,=HandlerADC ;mGKB

	b .
	b .
	b .
	b .
	b .
	b .
	b .
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
;	ldr pc,=HandlerDef
	;0xe0=EnterPWDN
	ldr pc,=EnterPWDN

	LTORG
	
HandlerFIQ 	HANDLER HandleFIQ
HandlerIRQ 	HANDLER HandleIRQ
HandlerUndef 	HANDLER HandleUndef
HandlerSWI 	HANDLER HandleSWI
HandlerDabort 	HANDLER HandleDabort
HandlerPabort 	HANDLER HandlePabort

;The following is used for the vectored interrupt.
;edit by plum from VHANDLER to HANDLER
HandlerADC 	HANDLER HandleADC
HandlerRTC 	HANDLER HandleRTC
HandlerUTXD1 	HANDLER HandleUTXD1
HandlerUTXD0 	HANDLER HandleUTXD0
HandlerSIO 		HANDLER HandleSIO
HandlerIIC 		HANDLER HandleIIC
HandlerURXD1 	HANDLER HandleURXD1
HandlerURXD0 	HANDLER HandleURXD0
HandlerTIMER5 	HANDLER HandleTIMER5
HandlerTIMER4 	HANDLER HandleTIMER4
HandlerTIMER3 	HANDLER HandleTIMER3
HandlerTIMER2 	HANDLER HandleTIMER2
HandlerTIMER1 	HANDLER HandleTIMER1
HandlerTIMER0 	HANDLER HandleTIMER0
HandlerUERR01 	HANDLER HandleUERR01
HandlerWDT 		HANDLER HandleWDT
HandlerBDMA1 	HANDLER HandleBDMA1
HandlerBDMA0 	HANDLER HandleBDMA0
HandlerZDMA1 	HANDLER HandleZDMA1
HandlerZDMA0 	HANDLER HandleZDMA0
HandlerTICK 	HANDLER HandleTICK
HandlerEINT4567 HANDLER HandleEINT4567
HandlerEINT3 	HANDLER HandleEINT3
HandlerEINT2 	HANDLER HandleEINT2
HandlerEINT1 	HANDLER HandleEINT1
HandlerEINT0 	HANDLER HandleEINT0


;del by plum
;HandlerDef ;INTMSK work-around
;	stmfd sp!,{r0,r1}
;	ldr r0,=I_PMST
;	ldr r1,[r0]
;	str r1,[r0]
;	ldmfd sp!,{r0,r1}
;	subs pc,lr,#4


IsrIRQ
	sub sp,sp,#4 ;reserved for PC
	stmfd sp!,{r8-r9}
	ldr r9,=I_ISPR
	ldr r9,[r9]
	cmp r9, #0x0 ;In some case, I_ISPR may be 0.
	beq %F2
	mov r8,#0x0
0
	movs r9,r9,lsr #1
	bcs %F1
	add r8,r8,#4
	b %B0
1
	ldr r9,=HandleADC
	add r9,r9,r8
	ldr r9,[r9]
	str r9,[sp,#8]
	ldmfd sp!,{r8-r9,pc}
2 
;	ldr r8,=I_PMST ;INTMSK work-around.	
;	ldr r9,[r8]
;	str r9,[r8]
; above del by plum

	ldmfd sp!,{r8-r9}
	add sp,sp,#4
	subs pc,lr,#4

;del by plum
;IsrFIQ
;	sub sp,sp,#4 ;reserved for PC
;	stmfd sp!,{r8-r9}
;	ldr r9,=I_ISPR
;	ldr r9,[r9]
;	cmp r9, #0x0 ;In some case, I_ISPR may be 0.
;	beq %F2
;	mov r8,#0x0
;0
;	movs r9,r9,lsr #1
;	bcs %F1
;	add r8,r8,#4
;	b %B0
;1
;	ldr r9,=HandleADC
;	add r9,r9,r8
;	ldr r9,[r9]
;	str r9,[sp,#8]
;	ldmfd sp!,{r8-r9,pc}
;2 
;	ldr r8,=I_PMST ;INTMSK work-around.
;	ldr r9,[r8]
;	str r9,[r8]
;	ldmfd sp!,{r8-r9}
;	add sp,sp,#4
;	subs pc,lr,#4
	
	
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;*	START					    *
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