option_boot.h

一个ADS下的ucos-II的移植代码,大家

;**************************OPTIONS*******************************

_RAM_STARTADDRESS  EQU    0x0d000000		;for sdram
;_RAM_STARTADDRESS  EQU    0x10000000		;for internal sram

_ISR_STARTADDRESS   EQU   0x0dffff00 		;GCS7:64M DRAM/SDRAM
;_ISR_STARTADDRESS   EQU   0x10001f00		;for internal sram


;BUSWIDTH; 16,32
                GBLA    BUSWIDTH
BUSWIDTH	SETA    32

;copy form flash to SDRAM
COPY_START EQU 0x1000
COPY_END   EQU 0x100000			;for sdram
;COPY_END   EQU 0x3000			;for internal sram



;This value has to be TRUE on ROM program.
;This value has to be FALSE in RAM program.
;                GBLL    PLLONSTART
;PLLONSTART      SETL    {TRUE}

	GBLA	PLLCLK
PLLCLK		SETA	60000000

	[	PLLCLK = 40000000	
M_DIV	EQU	0x48	;Fin=10MHz Fout=40MHz
P_DIV	EQU	0x3
S_DIV	EQU	0x2		
	]

	[	PLLCLK = 50000000	
M_DIV	EQU	0x2a	;Fin=10MHz Fout=50MHz
P_DIV	EQU	0x3
S_DIV	EQU	0x1	
	]

	[	PLLCLK = 60000000	
M_DIV	EQU	0x34	;Fin=10MHz Fout=60MHz
P_DIV	EQU	0x3
S_DIV	EQU	0x1
;M_DIV	EQU	0x34	;Fin=4MHz Fout=60MHz
;P_DIV	EQU	0x0
;S_DIV	EQU	0x1
;M_DIV	EQU	0x48	;Fin=3MHz Fout=60MHz
;P_DIV	EQU	0x0
;S_DIV	EQU	0x1
	]

	[	PLLCLK = 66000000	
M_DIV	EQU	0x3a	;Fin=10MHz Fout=75MHz
P_DIV	EQU	0x3
S_DIV	EQU	0x1		
	]

	[	PLLCLK = 75000000	
M_DIV	EQU	0x43	;Fin=10MHz Fout=75MHz
P_DIV	EQU	0x3
S_DIV	EQU	0x1		
	]
;************************************************
		END