9s08rx.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

mCMTCMD34_SB11:     equ    %100000000000
mCMTCMD34_SB12:     equ    %1000000000000
mCMTCMD34_SB13:     equ    %10000000000000
mCMTCMD34_SB14:     equ    %100000000000000
mCMTCMD34_SB15:     equ    %1000000000000000


;*** CMTCMD3 - CMT Modulator Data Register 3; 0x00000028 ***
CMTCMD3:            equ    $00000028                                ;*** CMTCMD3 - CMT Modulator Data Register 3; 0x00000028 ***


;*** CMTCMD4 - CMT Modulator Data Register 4; 0x00000029 ***
CMTCMD4:            equ    $00000029                                ;*** CMTCMD4 - CMT Modulator Data Register 4; 0x00000029 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
CMTCMD4_SB0:        equ    0                                         ; CMT Modulator Data Bit 0
CMTCMD4_SB1:        equ    1                                         ; CMT Modulator Data Bit 1
CMTCMD4_SB2:        equ    2                                         ; CMT Modulator Data Bit 2
CMTCMD4_SB3:        equ    3                                         ; CMT Modulator Data Bit 3
CMTCMD4_SB4:        equ    4                                         ; CMT Modulator Data Bit 4
CMTCMD4_SB5:        equ    5                                         ; CMT Modulator Data Bit 5
CMTCMD4_SB6:        equ    6                                         ; CMT Modulator Data Bit 6
CMTCMD4_SB7:        equ    7                                         ; CMT Modulator Data Bit 7
; bit position masks
mCMTCMD4_SB0:       equ    %00000001
mCMTCMD4_SB1:       equ    %00000010
mCMTCMD4_SB2:       equ    %00000100
mCMTCMD4_SB3:       equ    %00001000
mCMTCMD4_SB4:       equ    %00010000
mCMTCMD4_SB5:       equ    %00100000
mCMTCMD4_SB6:       equ    %01000000
mCMTCMD4_SB7:       equ    %10000000


;*** IRQSC - Interrupt Request Status and Control Register; 0x0000002A ***
IRQSC:              equ    $0000002A                                ;*** IRQSC - Interrupt Request Status and Control Register; 0x0000002A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
IRQSC_IRQMOD:       equ    0                                         ; IRQ Detection Mode
IRQSC_IRQIE:        equ    1                                         ; IRQ Interrupt Enable
IRQSC_IRQACK:       equ    2                                         ; IRQ Acknowledge
IRQSC_IRQF:         equ    3                                         ; IRQ Flag
IRQSC_IRQPE:        equ    4                                         ; IRQ Pin Enable
IRQSC_IRQEDG:       equ    5                                         ; Interrupt Request (IRQ) Edge Select
; bit position masks
mIRQSC_IRQMOD:      equ    %00000001
mIRQSC_IRQIE:       equ    %00000010
mIRQSC_IRQACK:      equ    %00000100
mIRQSC_IRQF:        equ    %00001000
mIRQSC_IRQPE:       equ    %00010000
mIRQSC_IRQEDG:      equ    %00100000


;*** ACMP1SC - Analog Comparator Status and Control Register; 0x0000002B ***
ACMP1SC:            equ    $0000002B                                ;*** ACMP1SC - Analog Comparator Status and Control Register; 0x0000002B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
ACMP1SC_ACMOD0:     equ    0                                         ; Analog Comparator Mode Bit 0
ACMP1SC_ACMOD1:     equ    1                                         ; Analog Comparator Mode Bit 1
ACMP1SC_ACO:        equ    3                                         ; Analog Comparator Output
ACMP1SC_ACIE:       equ    4                                         ; Analog Comparator Interrupt Enable
ACMP1SC_ACF:        equ    5                                         ; Analog Comparator Flag
ACMP1SC_ACBGS:      equ    6                                         ; Analog Comparator Bandgap Select
ACMP1SC_ACME:       equ    7                                         ; Analog Comparator Module Enable
; bit position masks
mACMP1SC_ACMOD0:    equ    %00000001
mACMP1SC_ACMOD1:    equ    %00000010
mACMP1SC_ACO:       equ    %00001000
mACMP1SC_ACIE:      equ    %00010000
mACMP1SC_ACF:       equ    %00100000
mACMP1SC_ACBGS:     equ    %01000000
mACMP1SC_ACME:      equ    %10000000


;*** TPM1SC - TPM1 Timer Status and Control Register; 0x00000030 ***
TPM1SC:             equ    $00000030                                ;*** TPM1SC - TPM1 Timer Status and Control Register; 0x00000030 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1SC_PS0:         equ    0                                         ; Prescale Divisor Select Bit 0
TPM1SC_PS1:         equ    1                                         ; Prescale Divisor Select Bit 1
TPM1SC_PS2:         equ    2                                         ; Prescale Divisor Select Bit 2
TPM1SC_CLKSA:       equ    3                                         ; Clock Source Select A
TPM1SC_CLKSB:       equ    4                                         ; Clock Source Select B
TPM1SC_CPWMS:       equ    5                                         ; Center-Aligned PWM Select
TPM1SC_TOIE:        equ    6                                         ; Timer Overflow Interrupt Enable
TPM1SC_TOF:         equ    7                                         ; Timer Overflow Flag
; bit position masks
mTPM1SC_PS0:        equ    %00000001
mTPM1SC_PS1:        equ    %00000010
mTPM1SC_PS2:        equ    %00000100
mTPM1SC_CLKSA:      equ    %00001000
mTPM1SC_CLKSB:      equ    %00010000
mTPM1SC_CPWMS:      equ    %00100000
mTPM1SC_TOIE:       equ    %01000000
mTPM1SC_TOF:        equ    %10000000


;*** TPM1CNT - TPM1 Counter Register; 0x00000031 ***
TPM1CNT:            equ    $00000031                                ;*** TPM1CNT - TPM1 Counter Register; 0x00000031 ***


;*** TPM1CNTH - TPM1 Counter Register High; 0x00000031 ***
TPM1CNTH:           equ    $00000031                                ;*** TPM1CNTH - TPM1 Counter Register High; 0x00000031 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1CNTH_BIT8:      equ    0                                         ; TPM1 Counter Bit 8
TPM1CNTH_BIT9:      equ    1                                         ; TPM1 Counter Bit 9
TPM1CNTH_BIT10:     equ    2                                         ; TPM1 Counter Bit 10
TPM1CNTH_BIT11:     equ    3                                         ; TPM1 Counter Bit 11
TPM1CNTH_BIT12:     equ    4                                         ; TPM1 Counter Bit 12
TPM1CNTH_BIT13:     equ    5                                         ; TPM1 Counter Bit 13
TPM1CNTH_BIT14:     equ    6                                         ; TPM1 Counter Bit 14
TPM1CNTH_BIT15:     equ    7                                         ; TPM1 Counter Bit 15
; bit position masks
mTPM1CNTH_BIT8:     equ    %00000001
mTPM1CNTH_BIT9:     equ    %00000010
mTPM1CNTH_BIT10:    equ    %00000100
mTPM1CNTH_BIT11:    equ    %00001000
mTPM1CNTH_BIT12:    equ    %00010000
mTPM1CNTH_BIT13:    equ    %00100000
mTPM1CNTH_BIT14:    equ    %01000000
mTPM1CNTH_BIT15:    equ    %10000000


;*** TPM1CNTL - TPM1 Counter Register Low; 0x00000032 ***
TPM1CNTL:           equ    $00000032                                ;*** TPM1CNTL - TPM1 Counter Register Low; 0x00000032 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1CNTL_BIT0:      equ    0                                         ; TPM1 Counter Bit 0
TPM1CNTL_BIT1:      equ    1                                         ; TPM1 Counter Bit 1
TPM1CNTL_BIT2:      equ    2                                         ; TPM1 Counter Bit 2
TPM1CNTL_BIT3:      equ    3                                         ; TPM1 Counter Bit 3
TPM1CNTL_BIT4:      equ    4                                         ; TPM1 Counter Bit 4
TPM1CNTL_BIT5:      equ    5                                         ; TPM1 Counter Bit 5
TPM1CNTL_BIT6:      equ    6                                         ; TPM1 Counter Bit 6
TPM1CNTL_BIT7:      equ    7                                         ; TPM1 Counter Bit 7
; bit position masks
mTPM1CNTL_BIT0:     equ    %00000001
mTPM1CNTL_BIT1:     equ    %00000010
mTPM1CNTL_BIT2:     equ    %00000100
mTPM1CNTL_BIT3:     equ    %00001000
mTPM1CNTL_BIT4:     equ    %00010000
mTPM1CNTL_BIT5:     equ    %00100000
mTPM1CNTL_BIT6:     equ    %01000000
mTPM1CNTL_BIT7:     equ    %10000000


;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0x00000033 ***
TPM1MOD:            equ    $00000033                                ;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0x00000033 ***


;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0x00000033 ***
TPM1MODH:           equ    $00000033                                ;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0x00000033 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1MODH_BIT8:      equ    0                                         ; Timer Counter Modulo Bit 8
TPM1MODH_BIT9:      equ    1                                         ; Timer Counter Modulo Bit 9
TPM1MODH_BIT10:     equ    2                                         ; Timer Counter Modulo Bit 10
TPM1MODH_BIT11:     equ    3                                         ; Timer Counter Modulo Bit 11
TPM1MODH_BIT12:     equ    4                                         ; Timer Counter Modulo Bit 12
TPM1MODH_BIT13:     equ    5                                         ; Timer Counter Modulo Bit 13
TPM1MODH_BIT14:     equ    6                                         ; Timer Counter Modulo Bit 14
TPM1MODH_BIT15:     equ    7                                         ; Timer Counter Modulo Bit 15
; bit position masks
mTPM1MODH_BIT8:     equ    %00000001
mTPM1MODH_BIT9:     equ    %00000010
mTPM1MODH_BIT10:    equ    %00000100
mTPM1MODH_BIT11:    equ    %00001000
mTPM1MODH_BIT12:    equ    %00010000
mTPM1MODH_BIT13:    equ    %00100000
mTPM1MODH_BIT14:    equ    %01000000
mTPM1MODH_BIT15:    equ    %10000000


;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0x00000034 ***
TPM1MODL:           equ    $00000034                                ;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0x00000034 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1MODL_BIT0:      equ    0                                         ; Timer Counter Modulo Bit 0
TPM1MODL_BIT1:      equ    1                                         ; Timer Counter Modulo Bit 1
TPM1MODL_BIT2:      equ    2                                         ; Timer Counter Modulo Bit 2
TPM1MODL_BIT3:      equ    3                                         ; Timer Counter Modulo Bit 3
TPM1MODL_BIT4:      equ    4                                         ; Timer Counter Modulo Bit 4
TPM1MODL_BIT5:      equ    5                                         ; Timer Counter Modulo Bit 5
TPM1MODL_BIT6:      equ    6                                         ; Timer Counter Modulo Bit 6
TPM1MODL_BIT7:      equ    7                                         ; Timer Counter Modulo Bit 7
; bit position masks
mTPM1MODL_BIT0:     equ    %00000001
mTPM1MODL_BIT1:     equ    %00000010
mTPM1MODL_BIT2:     equ    %00000100
mTPM1MODL_BIT3:     equ    %00001000
mTPM1MODL_BIT4:     equ    %00010000
mTPM1MODL_BIT5:     equ    %00100000
mTPM1MODL_BIT6:     equ    %01000000
mTPM1MODL_BIT7:     equ    %10000000


;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000035 ***
TPM1C0SC:           equ    $00000035                                ;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000035 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1C0SC_ELS0A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C0SC_ELS0B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C0SC_MS0A:      equ    4                                         ; Mode Select A for TPM1 Channel 0
TPM1C0SC_MS0B:      equ    5                                         ; Mode Select B for TPM1 Channel 0
TPM1C0SC_CH0IE:     equ    6                                         ; Channel 0 Interrupt Enable
TPM1C0SC_CH0F:      equ    7                                         ; Channel 0 Flag
; bit position masks
mTPM1C0SC_ELS0A:    equ    %00000100
mTPM1C0SC_ELS0B:    equ    %00001000
mTPM1C0SC_MS0A:     equ    %00010000
mTPM1C0SC_MS0B:     equ    %00100000
mTPM1C0SC_CH0IE:    equ    %01000000
mTPM1C0SC_CH0F:     equ    %10000000


;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0x00000036 ***
TPM1C0V:            equ    $00000036                                ;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0x00000036 ***


;*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0x00000036 ***
TPM1C0VH:           equ    $00000036                                ;*** TPM1C0VH - TPM1 Timer C