📄 9s08rx.inc
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mKBI2SC_KBIE: equ %00000010
mKBI2SC_KBACK: equ %00000100
mKBI2SC_KBF: equ %00001000
;*** KBI2PE - KBI2 Pin Enable Register; 0x00000017 ***
KBI2PE: equ $00000017 ;*** KBI2PE - KBI2 Pin Enable Register; 0x00000017 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
KBI2PE_KBIPE0: equ 0 ; Keyboard Pin Enable for Port C Bit 0
KBI2PE_KBIPE1: equ 1 ; Keyboard Pin Enable for Port C Bit 1
KBI2PE_KBIPE2: equ 2 ; Keyboard Pin Enable for Port C Bit 2
KBI2PE_KBIPE3: equ 3 ; Keyboard Pin Enable for Port C Bit 3
; bit position masks
mKBI2PE_KBIPE0: equ %00000001
mKBI2PE_KBIPE1: equ %00000010
mKBI2PE_KBIPE2: equ %00000100
mKBI2PE_KBIPE3: equ %00001000
;*** SCI1BD - SCI1 Baud Rate Register; 0x00000018 ***
SCI1BD: equ $00000018 ;*** SCI1BD - SCI1 Baud Rate Register; 0x00000018 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1BD_SBR0: equ 0 ; Baud Rate Modulo Divisor Bit 0
SCI1BD_SBR1: equ 1 ; Baud Rate Modulo Divisor Bit 1
SCI1BD_SBR2: equ 2 ; Baud Rate Modulo Divisor Bit 2
SCI1BD_SBR3: equ 3 ; Baud Rate Modulo Divisor Bit 3
SCI1BD_SBR4: equ 4 ; Baud Rate Modulo Divisor Bit 4
SCI1BD_SBR5: equ 5 ; Baud Rate Modulo Divisor Bit 5
SCI1BD_SBR6: equ 6 ; Baud Rate Modulo Divisor Bit 6
SCI1BD_SBR7: equ 7 ; Baud Rate Modulo Divisor Bit 7
SCI1BD_SBR8: equ 8 ; Baud Rate Modulo Divisor Bit 8
SCI1BD_SBR9: equ 9 ; Baud Rate Modulo Divisor Bit 9
SCI1BD_SBR10: equ 10 ; Baud Rate Modulo Divisor Bit 10
SCI1BD_SBR11: equ 11 ; Baud Rate Modulo Divisor Bit 11
SCI1BD_SBR12: equ 12 ; Baud Rate Modulo Divisor Bit 12
; bit position masks
mSCI1BD_SBR0: equ %00000001
mSCI1BD_SBR1: equ %00000010
mSCI1BD_SBR2: equ %00000100
mSCI1BD_SBR3: equ %00001000
mSCI1BD_SBR4: equ %00010000
mSCI1BD_SBR5: equ %00100000
mSCI1BD_SBR6: equ %01000000
mSCI1BD_SBR7: equ %10000000
mSCI1BD_SBR8: equ %100000000
mSCI1BD_SBR9: equ %1000000000
mSCI1BD_SBR10: equ %10000000000
mSCI1BD_SBR11: equ %100000000000
mSCI1BD_SBR12: equ %1000000000000
;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000018 ***
SCI1BDH: equ $00000018 ;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000018 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1BDH_SBR8: equ 0 ; Baud Rate Modulo Divisor Bit 8
SCI1BDH_SBR9: equ 1 ; Baud Rate Modulo Divisor Bit 9
SCI1BDH_SBR10: equ 2 ; Baud Rate Modulo Divisor Bit 10
SCI1BDH_SBR11: equ 3 ; Baud Rate Modulo Divisor Bit 11
SCI1BDH_SBR12: equ 4 ; Baud Rate Modulo Divisor Bit 12
; bit position masks
mSCI1BDH_SBR8: equ %00000001
mSCI1BDH_SBR9: equ %00000010
mSCI1BDH_SBR10: equ %00000100
mSCI1BDH_SBR11: equ %00001000
mSCI1BDH_SBR12: equ %00010000
;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000019 ***
SCI1BDL: equ $00000019 ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000019 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1BDL_SBR0: equ 0 ; Baud Rate Modulo Divisor Bit 0
SCI1BDL_SBR1: equ 1 ; Baud Rate Modulo Divisor Bit 1
SCI1BDL_SBR2: equ 2 ; Baud Rate Modulo Divisor Bit 2
SCI1BDL_SBR3: equ 3 ; Baud Rate Modulo Divisor Bit 3
SCI1BDL_SBR4: equ 4 ; Baud Rate Modulo Divisor Bit 4
SCI1BDL_SBR5: equ 5 ; Baud Rate Modulo Divisor Bit 5
SCI1BDL_SBR6: equ 6 ; Baud Rate Modulo Divisor Bit 6
SCI1BDL_SBR7: equ 7 ; Baud Rate Modulo Divisor Bit 7
; bit position masks
mSCI1BDL_SBR0: equ %00000001
mSCI1BDL_SBR1: equ %00000010
mSCI1BDL_SBR2: equ %00000100
mSCI1BDL_SBR3: equ %00001000
mSCI1BDL_SBR4: equ %00010000
mSCI1BDL_SBR5: equ %00100000
mSCI1BDL_SBR6: equ %01000000
mSCI1BDL_SBR7: equ %10000000
;*** SCI1C1 - SCI1 Control Register 1; 0x0000001A ***
SCI1C1: equ $0000001A ;*** SCI1C1 - SCI1 Control Register 1; 0x0000001A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1C1_PT: equ 0 ; Parity Type
SCI1C1_PE: equ 1 ; Parity Enable
SCI1C1_ILT: equ 2 ; Idle Line Type Select
SCI1C1_WAKE: equ 3 ; Receiver Wakeup Method Select
SCI1C1_M: equ 4 ; 9-Bit or 8-Bit Mode Select
SCI1C1_RSRC: equ 5 ; Receiver Source Select
SCI1C1_SCI1SWAI: equ 6 ; SCI1 Stops in Wait Mode
SCI1C1_LOOPS: equ 7 ; Loop Mode Select
; bit position masks
mSCI1C1_PT: equ %00000001
mSCI1C1_PE: equ %00000010
mSCI1C1_ILT: equ %00000100
mSCI1C1_WAKE: equ %00001000
mSCI1C1_M: equ %00010000
mSCI1C1_RSRC: equ %00100000
mSCI1C1_SCI1SWAI: equ %01000000
mSCI1C1_LOOPS: equ %10000000
;*** SCI1C2 - SCI1 Control Register 2; 0x0000001B ***
SCI1C2: equ $0000001B ;*** SCI1C2 - SCI1 Control Register 2; 0x0000001B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1C2_SBK: equ 0 ; Send Break
SCI1C2_RWU: equ 1 ; Receiver Wakeup Control
SCI1C2_RE: equ 2 ; Receiver Enable
SCI1C2_TE: equ 3 ; Transmitter Enable
SCI1C2_ILIE: equ 4 ; Idle Line Interrupt Enable (for IDLE)
SCI1C2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF)
SCI1C2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC)
SCI1C2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE)
; bit position masks
mSCI1C2_SBK: equ %00000001
mSCI1C2_RWU: equ %00000010
mSCI1C2_RE: equ %00000100
mSCI1C2_TE: equ %00001000
mSCI1C2_ILIE: equ %00010000
mSCI1C2_RIE: equ %00100000
mSCI1C2_TCIE: equ %01000000
mSCI1C2_TIE: equ %10000000
;*** SCI1S1 - SCI1 Status Register 1; 0x0000001C ***
SCI1S1: equ $0000001C ;*** SCI1S1 - SCI1 Status Register 1; 0x0000001C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1S1_PF: equ 0 ; Parity Error Flag
SCI1S1_FE: equ 1 ; Framing Error Flag
SCI1S1_NF: equ 2 ; Noise Flag
SCI1S1_OR: equ 3 ; Receiver Overrun Flag
SCI1S1_IDLE: equ 4 ; Idle Line Flag
SCI1S1_RDRF: equ 5 ; Receive Data Register Full Flag
SCI1S1_TC: equ 6 ; Transmission Complete Flag
SCI1S1_TDRE: equ 7 ; Transmit Data Register Empty Flag
; bit position masks
mSCI1S1_PF: equ %00000001
mSCI1S1_FE: equ %00000010
mSCI1S1_NF: equ %00000100
mSCI1S1_OR: equ %00001000
mSCI1S1_IDLE: equ %00010000
mSCI1S1_RDRF: equ %00100000
mSCI1S1_TC: equ %01000000
mSCI1S1_TDRE: equ %10000000
;*** SCI1S2 - SCI1 Status Register 2; 0x0000001D ***
SCI1S2: equ $0000001D ;*** SCI1S2 - SCI1 Status Register 2; 0x0000001D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1S2_RAF: equ 0 ; Receiver Active Flag
; bit position masks
mSCI1S2_RAF: equ %00000001
;*** SCI1C3 - SCI1 Control Register 3; 0x0000001E ***
SCI1C3: equ $0000001E ;*** SCI1C3 - SCI1 Control Register 3; 0x0000001E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1C3_PEIE: equ 0 ; Parity Error Interrupt Enable
SCI1C3_FEIE: equ 1 ; Framing Error Interrupt Enable
SCI1C3_NEIE: equ 2 ; Noise Error Interrupt Enable
SCI1C3_ORIE: equ 3 ; Overrun Interrupt Enable
SCI1C3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode
SCI1C3_T8: equ 6 ; Ninth Data Bit for Transmitter
SCI1C3_R8: equ 7 ; Ninth Data Bit for Receiver
; bit position masks
mSCI1C3_PEIE: equ %00000001
mSCI1C3_FEIE: equ %00000010
mSCI1C3_NEIE: equ %00000100
mSCI1C3_ORIE: equ %00001000
mSCI1C3_TXDIR: equ %00100000
mSCI1C3_T8: equ %01000000
mSCI1C3_R8: equ %10000000
;*** SCI1DRL - SCI1 Data Register; 0x0000001F ***
SCI1DRL: equ $0000001F ;*** SCI1DRL - SCI1 Data Register; 0x0000001F ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
SCI1DRL_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCI1DRL_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCI1DRL_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCI1DRL_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCI1DRL_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCI1DRL_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCI1DRL_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCI1DRL_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCI1DRL_R0_T0: equ %00000001
mSCI1DRL_R1_T1: equ %00000010
mSCI1DRL_R2_T2: equ %00000100
mSCI1DRL_R3_T3: equ %00001000
mSCI1DRL_R4_T4: equ %00010000
mSCI1DRL_R5_T5: equ %00100000
mSCI1DRL_R6_T6: equ %01000000
mSCI1DRL_R7_T7: equ %10000000
;*** CMTCG1 - Carrier Generator Data Register 1; 0x00000020 ***
CMTCG1: equ $00000020 ;*** CMTCG1 - Carrier Generator Data Register 1; 0x00000020 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
CMTCG1_PL0: equ 0 ; Primary Carrier Low Time Data Value Bit 0
CMTCG1_PL1: equ 1 ; Primary Carrier Low Time Data Value Bit 1
CMTCG1_PL2: equ 2 ; Primary Carrier Low Time Data Value Bit 2
CMTCG1_PL3: equ 3 ; Primary Carrier Low Time Data Value Bit 3
CMTCG1_PL4: equ 4 ; Primary Carrier Low Time Data Value Bit 4
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