mc9s08aw60.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

; bit position masks
mAD1CVH_ADCV8:      equ    %00000001
mAD1CVH_ADCV9:      equ    %00000010


;*** AD1CVL - Compare Value Register Low; 0x00000015 ***
AD1CVL:             equ    $00000015                                ;*** AD1CVL - Compare Value Register Low; 0x00000015 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1CVL_ADCV0:       equ    0                                         ; Compare Function Value 0
AD1CVL_ADCV1:       equ    1                                         ; Compare Function Value 1
AD1CVL_ADCV2:       equ    2                                         ; Compare Function Value 2
AD1CVL_ADCV3:       equ    3                                         ; Compare Function Value 3
AD1CVL_ADCV4:       equ    4                                         ; Compare Function Value 4
AD1CVL_ADCV5:       equ    5                                         ; Compare Function Value 5
AD1CVL_ADCV6:       equ    6                                         ; Compare Function Value 6
AD1CVL_ADCV7:       equ    7                                         ; Compare Function Value 7
; bit position masks
mAD1CVL_ADCV0:      equ    %00000001
mAD1CVL_ADCV1:      equ    %00000010
mAD1CVL_ADCV2:      equ    %00000100
mAD1CVL_ADCV3:      equ    %00001000
mAD1CVL_ADCV4:      equ    %00010000
mAD1CVL_ADCV5:      equ    %00100000
mAD1CVL_ADCV6:      equ    %01000000
mAD1CVL_ADCV7:      equ    %10000000


;*** AD1CFG - Configuration Register; 0x00000016 ***
AD1CFG:             equ    $00000016                                ;*** AD1CFG - Configuration Register; 0x00000016 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1CFG_ADICLK0:     equ    0                                         ; Input Clock Select Bit 0
AD1CFG_ADICLK1:     equ    1                                         ; Input Clock Select Bit 1
AD1CFG_MODE0:       equ    2                                         ; Conversion Mode Selection Bit 0
AD1CFG_MODE1:       equ    3                                         ; Conversion Mode Selection Bit 1
AD1CFG_ADLSMP:      equ    4                                         ; Long Sample Time Configuration
AD1CFG_ADIV0:       equ    5                                         ; Clock Divide Select Bit 0
AD1CFG_ADIV1:       equ    6                                         ; Clock Divide Select Bit 1
AD1CFG_ADLPC:       equ    7                                         ; Low Power Configuration
; bit position masks
mAD1CFG_ADICLK0:    equ    %00000001
mAD1CFG_ADICLK1:    equ    %00000010
mAD1CFG_MODE0:      equ    %00000100
mAD1CFG_MODE1:      equ    %00001000
mAD1CFG_ADLSMP:     equ    %00010000
mAD1CFG_ADIV0:      equ    %00100000
mAD1CFG_ADIV1:      equ    %01000000
mAD1CFG_ADLPC:      equ    %10000000


;*** APCTL1 - ADC10 Pin Control 1 Register; 0x00000017 ***
APCTL1:             equ    $00000017                                ;*** APCTL1 - ADC10 Pin Control 1 Register; 0x00000017 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
APCTL1_ADPC0:       equ    0                                         ; ADC10 Pin Control 0
APCTL1_ADPC1:       equ    1                                         ; ADC10 Pin Control 1
APCTL1_ADPC2:       equ    2                                         ; ADC10 Pin Control 2
APCTL1_ADPC3:       equ    3                                         ; ADC10 Pin Control 3
APCTL1_ADPC4:       equ    4                                         ; ADC10 Pin Control 4
APCTL1_ADPC5:       equ    5                                         ; ADC10 Pin Control 5
APCTL1_ADPC6:       equ    6                                         ; ADC10 Pin Control 6
APCTL1_ADPC7:       equ    7                                         ; ADC10 Pin Control 7
; bit position masks
mAPCTL1_ADPC0:      equ    %00000001
mAPCTL1_ADPC1:      equ    %00000010
mAPCTL1_ADPC2:      equ    %00000100
mAPCTL1_ADPC3:      equ    %00001000
mAPCTL1_ADPC4:      equ    %00010000
mAPCTL1_ADPC5:      equ    %00100000
mAPCTL1_ADPC6:      equ    %01000000
mAPCTL1_ADPC7:      equ    %10000000


;*** APCTL2 - ADC10 Pin Control 2 Register; 0x00000018 ***
APCTL2:             equ    $00000018                                ;*** APCTL2 - ADC10 Pin Control 2 Register; 0x00000018 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
APCTL2_ADPC8:       equ    0                                         ; ADC10 Pin Control 8
APCTL2_ADPC9:       equ    1                                         ; ADC10 Pin Control 9
APCTL2_ADPC10:      equ    2                                         ; ADC10 Pin Control 10
APCTL2_ADPC11:      equ    3                                         ; ADC10 Pin Control 11
APCTL2_ADPC12:      equ    4                                         ; ADC10 Pin Control 12
APCTL2_ADPC13:      equ    5                                         ; ADC10 Pin Control 13
APCTL2_ADPC14:      equ    6                                         ; ADC10 Pin Control 14
APCTL2_ADPC15:      equ    7                                         ; ADC10 Pin Control 15
; bit position masks
mAPCTL2_ADPC8:      equ    %00000001
mAPCTL2_ADPC9:      equ    %00000010
mAPCTL2_ADPC10:     equ    %00000100
mAPCTL2_ADPC11:     equ    %00001000
mAPCTL2_ADPC12:     equ    %00010000
mAPCTL2_ADPC13:     equ    %00100000
mAPCTL2_ADPC14:     equ    %01000000
mAPCTL2_ADPC15:     equ    %10000000


;*** APCTL3 - ADC10 Pin Control 3 Register; 0x00000019 ***
APCTL3:             equ    $00000019                                ;*** APCTL3 - ADC10 Pin Control 3 Register; 0x00000019 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
APCTL3_ADPC16:      equ    0                                         ; ADC10 Pin Control 16
APCTL3_ADPC17:      equ    1                                         ; ADC10 Pin Control 17
APCTL3_ADPC18:      equ    2                                         ; ADC10 Pin Control 18
APCTL3_ADPC19:      equ    3                                         ; ADC10 Pin Control 19
APCTL3_ADPC20:      equ    4                                         ; ADC10 Pin Control 20
APCTL3_ADPC21:      equ    5                                         ; ADC10 Pin Control 21
APCTL3_ADPC22:      equ    6                                         ; ADC10 Pin Control 22
APCTL3_ADPC23:      equ    7                                         ; ADC10 Pin Control 23
; bit position masks
mAPCTL3_ADPC16:     equ    %00000001
mAPCTL3_ADPC17:     equ    %00000010
mAPCTL3_ADPC18:     equ    %00000100
mAPCTL3_ADPC19:     equ    %00001000
mAPCTL3_ADPC20:     equ    %00010000
mAPCTL3_ADPC21:     equ    %00100000
mAPCTL3_ADPC22:     equ    %01000000
mAPCTL3_ADPC23:     equ    %10000000


;*** IRQSC - Interrupt Request Status and Control Register; 0x0000001C ***
IRQSC:              equ    $0000001C                                ;*** IRQSC - Interrupt Request Status and Control Register; 0x0000001C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
IRQSC_IRQMOD:       equ    0                                         ; IRQ Detection Mode
IRQSC_IRQIE:        equ    1                                         ; IRQ Interrupt Enable
IRQSC_IRQACK:       equ    2                                         ; IRQ Acknowledge
IRQSC_IRQF:         equ    3                                         ; IRQ Flag
IRQSC_IRQPE:        equ    4                                         ; IRQ Pin Enable
IRQSC_IRQEDG:       equ    5                                         ; Interrupt Request (IRQ) Edge Select
; bit position masks
mIRQSC_IRQMOD:      equ    %00000001
mIRQSC_IRQIE:       equ    %00000010
mIRQSC_IRQACK:      equ    %00000100
mIRQSC_IRQF:        equ    %00001000
mIRQSC_IRQPE:       equ    %00010000
mIRQSC_IRQEDG:      equ    %00100000


;*** KBI1SC - KBI1 Status and Control; 0x0000001E ***
KBI1SC:             equ    $0000001E                                ;*** KBI1SC - KBI1 Status and Control; 0x0000001E ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
KBI1SC_KBIMOD:      equ    0                                         ; Keyboard Detection Mode
KBI1SC_KBIE:        equ    1                                         ; Keyboard Interrupt Enable
KBI1SC_KBACK:       equ    2                                         ; Keyboard Interrupt Acknowledge
KBI1SC_KBF:         equ    3                                         ; Keyboard Interrupt Flag
KBI1SC_KBEDG4:      equ    4                                         ; Keyboard Edge Select for Port A Bit 4
KBI1SC_KBEDG5:      equ    5                                         ; Keyboard Edge Select for Port A Bit 5
KBI1SC_KBEDG6:      equ    6                                         ; Keyboard Edge Select for Port A Bit 6
KBI1SC_KBEDG7:      equ    7                                         ; Keyboard Edge Select for Port A Bit 7
; bit position masks
mKBI1SC_KBIMOD:     equ    %00000001
mKBI1SC_KBIE:       equ    %00000010
mKBI1SC_KBACK:      equ    %00000100
mKBI1SC_KBF:        equ    %00001000
mKBI1SC_KBEDG4:     equ    %00010000
mKBI1SC_KBEDG5:     equ    %00100000
mKBI1SC_KBEDG6:     equ    %01000000
mKBI1SC_KBEDG7:     equ    %10000000


;*** KBI1PE - KBI1 Pin Enable Register; 0x0000001F ***
KBI1PE:             equ    $0000001F                                ;*** KBI1PE - KBI1 Pin Enable Register; 0x0000001F ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
KBI1PE_KBIPE0:      equ    0                                         ; Keyboard Pin Enable for Port A Bit 0
KBI1PE_KBIPE1:      equ    1                                         ; Keyboard Pin Enable for Port A Bit 1
KBI1PE_KBIPE2:      equ    2                                         ; Keyboard Pin Enable for Port A Bit 2
KBI1PE_KBIPE3:      equ    3                                         ; Keyboard Pin Enable for Port A Bit 3
KBI1PE_KBIPE4:      equ    4                                         ; Keyboard Pin Enable for Port A Bit 4
KBI1PE_KBIPE5:      equ    5                                         ; Keyboard Pin Enable for Port A Bit 5
KBI1PE_KBIPE6:      equ    6                                         ; Keyboard Pin Enable for Port A Bit 6
KBI1PE_KBIPE7:      equ    7                                         ; Keyboard Pin Enable for Port A Bit 7
; bit position masks
mKBI1PE_KBIPE0:     equ    %00000001
mKBI1PE_KBIPE1:     equ    %00000010
mKBI1PE_KBIPE2:     equ    %00000100
mKBI1PE_KBIPE3:     equ    %00001000
mKBI1PE_KBIPE4:     equ    %00010000
mKBI1PE_KBIPE5:     equ    %00100000
mKBI1PE_KBIPE6:     equ    %01000000
mKBI1PE_KBIPE7:     equ    %10000000


;*** TPM1SC - TPM 1 Status and Control Register; 0x00000020 ***
TPM1SC:             equ    $00000020                                ;*** TPM1SC - TPM 1 Status and Control Register; 0x00000020 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
TPM1SC_PS0:         equ    0                                         ; Prescale Divisor Select Bit 0
TPM1SC_PS1:         equ    1                                         ; Prescale Divisor Select Bit 1
TPM1SC_PS2:         equ    2                                         ; Prescale Divisor Select Bit 2
TPM1SC_CLKSA:       equ    3                                         ; Clock Source Select A
TPM1SC_CLKSB:       equ    4                                         ; Clock Source Select B
TPM1SC_CPWMS:       equ    5                                         ; Center-Aligned PWM Select
TPM1SC_TOIE:        equ    6                                         ; Timer Overflow Interrupt Enable
TPM1SC_TOF:         equ    7                                         ; Timer Overflow Flag
; bit position masks
mTPM1SC_PS0:        equ    %00000001
mTPM1SC_PS1:        equ    %00000010
mTPM1SC_PS2:        equ    %00000100
mTPM1SC_CLKSA:      equ    %00001000
mTPM1SC_CLKSB:      equ    %00010000
mTPM1SC_CPWMS:      equ    %00100000
mTPM1SC_TOIE:       equ    %01000000
mTPM1SC_TOF:        equ    %10000000


;*** TPM1CNT - TPM 1 Counter Register; 0x00000021 ***
TPM1CNT:            equ    $00000021                                ;*** TPM1CNT - TPM 1 Counter Register; 0x00000021 ***


;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000021 ***
TPM1CNTH:           equ    $00000021                                ;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000021 ***


;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000022 ***
TPM1CNTL:           equ    $00000022                                ;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000022 ***


;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000023 ***
TPM1MOD:            equ    $00000023                                ;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000023 ***


;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000023 ***
TPM1MODH:           equ    $00000023                                ;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000023 ***


;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000024 ***
TPM1MODL:           equ    $00000024                                ;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000024 ***