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📄 mc9s08aw60.inc

📁 M68HC08及HCS08系列单片机bootloader引导程序源码/示例
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PTDDD_PTDDD7:       equ    7                                         ; Data Direction for Port D Bit 7
; bit position masks
mPTDDD_PTDDD0:      equ    %00000001
mPTDDD_PTDDD1:      equ    %00000010
mPTDDD_PTDDD2:      equ    %00000100
mPTDDD_PTDDD3:      equ    %00001000
mPTDDD_PTDDD4:      equ    %00010000
mPTDDD_PTDDD5:      equ    %00100000
mPTDDD_PTDDD6:      equ    %01000000
mPTDDD_PTDDD7:      equ    %10000000


;*** PTED - Port E Data Register; 0x00000008 ***
PTED:               equ    $00000008                                ;*** PTED - Port E Data Register; 0x00000008 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTED_PTED0:         equ    0                                         ; Port E Data Register Bit 0
PTED_PTED1:         equ    1                                         ; Port E Data Register Bit 1
PTED_PTED2:         equ    2                                         ; Port E Data Register Bit 2
PTED_PTED3:         equ    3                                         ; Port E Data Register Bit 3
PTED_PTED4:         equ    4                                         ; Port E Data Register Bit 4
PTED_PTED5:         equ    5                                         ; Port E Data Register Bit 5
PTED_PTED6:         equ    6                                         ; Port E Data Register Bit 6
PTED_PTED7:         equ    7                                         ; Port E Data Register Bit 7
; bit position masks
mPTED_PTED0:        equ    %00000001
mPTED_PTED1:        equ    %00000010
mPTED_PTED2:        equ    %00000100
mPTED_PTED3:        equ    %00001000
mPTED_PTED4:        equ    %00010000
mPTED_PTED5:        equ    %00100000
mPTED_PTED6:        equ    %01000000
mPTED_PTED7:        equ    %10000000


;*** PTEDD - Data Direction Register E; 0x00000009 ***
PTEDD:              equ    $00000009                                ;*** PTEDD - Data Direction Register E; 0x00000009 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTEDD_PTEDD0:       equ    0                                         ; Data Direction for Port E Bit 0
PTEDD_PTEDD1:       equ    1                                         ; Data Direction for Port E Bit 1
PTEDD_PTEDD2:       equ    2                                         ; Data Direction for Port E Bit 2
PTEDD_PTEDD3:       equ    3                                         ; Data Direction for Port E Bit 3
PTEDD_PTEDD4:       equ    4                                         ; Data Direction for Port E Bit 4
PTEDD_PTEDD5:       equ    5                                         ; Data Direction for Port E Bit 5
PTEDD_PTEDD6:       equ    6                                         ; Data Direction for Port E Bit 6
PTEDD_PTEDD7:       equ    7                                         ; Data Direction for Port E Bit 7
; bit position masks
mPTEDD_PTEDD0:      equ    %00000001
mPTEDD_PTEDD1:      equ    %00000010
mPTEDD_PTEDD2:      equ    %00000100
mPTEDD_PTEDD3:      equ    %00001000
mPTEDD_PTEDD4:      equ    %00010000
mPTEDD_PTEDD5:      equ    %00100000
mPTEDD_PTEDD6:      equ    %01000000
mPTEDD_PTEDD7:      equ    %10000000


;*** PTFD - Port F Data Register; 0x0000000A ***
PTFD:               equ    $0000000A                                ;*** PTFD - Port F Data Register; 0x0000000A ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTFD_PTFD0:         equ    0                                         ; Port F Data Register Bit 0
PTFD_PTFD1:         equ    1                                         ; Port F Data Register Bit 1
PTFD_PTFD2:         equ    2                                         ; Port F Data Register Bit 2
PTFD_PTFD3:         equ    3                                         ; Port F Data Register Bit 3
PTFD_PTFD4:         equ    4                                         ; Port F Data Register Bit 4
PTFD_PTFD5:         equ    5                                         ; Port F Data Register Bit 5
PTFD_PTFD6:         equ    6                                         ; Port F Data Register Bit 6
PTFD_PTFD7:         equ    7                                         ; Port F Data Register Bit 7
; bit position masks
mPTFD_PTFD0:        equ    %00000001
mPTFD_PTFD1:        equ    %00000010
mPTFD_PTFD2:        equ    %00000100
mPTFD_PTFD3:        equ    %00001000
mPTFD_PTFD4:        equ    %00010000
mPTFD_PTFD5:        equ    %00100000
mPTFD_PTFD6:        equ    %01000000
mPTFD_PTFD7:        equ    %10000000


;*** PTFDD - Data Direction Register F; 0x0000000B ***
PTFDD:              equ    $0000000B                                ;*** PTFDD - Data Direction Register F; 0x0000000B ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTFDD_PTFDD0:       equ    0                                         ; Data Direction for Port F Bit 0
PTFDD_PTFDD1:       equ    1                                         ; Data Direction for Port F Bit 1
PTFDD_PTFDD2:       equ    2                                         ; Data Direction for Port F Bit 2
PTFDD_PTFDD3:       equ    3                                         ; Data Direction for Port F Bit 3
PTFDD_PTFDD4:       equ    4                                         ; Data Direction for Port F Bit 4
PTFDD_PTFDD5:       equ    5                                         ; Data Direction for Port F Bit 5
PTFDD_PTFDD6:       equ    6                                         ; Data Direction for Port F Bit 6
PTFDD_PTFDD7:       equ    7                                         ; Data Direction for Port F Bit 7
; bit position masks
mPTFDD_PTFDD0:      equ    %00000001
mPTFDD_PTFDD1:      equ    %00000010
mPTFDD_PTFDD2:      equ    %00000100
mPTFDD_PTFDD3:      equ    %00001000
mPTFDD_PTFDD4:      equ    %00010000
mPTFDD_PTFDD5:      equ    %00100000
mPTFDD_PTFDD6:      equ    %01000000
mPTFDD_PTFDD7:      equ    %10000000


;*** PTGD - Port G Data Register; 0x0000000C ***
PTGD:               equ    $0000000C                                ;*** PTGD - Port G Data Register; 0x0000000C ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTGD_PTGD0:         equ    0                                         ; Port G Data Register Bit 0
PTGD_PTGD1:         equ    1                                         ; Port G Data Register Bit 1
PTGD_PTGD2:         equ    2                                         ; Port G Data Register Bit 2
PTGD_PTGD3:         equ    3                                         ; Port G Data Register Bit 3
PTGD_PTGD4:         equ    4                                         ; Port G Data Register Bit 4
PTGD_PTGD5:         equ    5                                         ; Port G Data Register Bit 5
PTGD_PTGD6:         equ    6                                         ; Port G Data Register Bit 6
; bit position masks
mPTGD_PTGD0:        equ    %00000001
mPTGD_PTGD1:        equ    %00000010
mPTGD_PTGD2:        equ    %00000100
mPTGD_PTGD3:        equ    %00001000
mPTGD_PTGD4:        equ    %00010000
mPTGD_PTGD5:        equ    %00100000
mPTGD_PTGD6:        equ    %01000000


;*** PTGDD - Data Direction Register G; 0x0000000D ***
PTGDD:              equ    $0000000D                                ;*** PTGDD - Data Direction Register G; 0x0000000D ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
PTGDD_PTGDD0:       equ    0                                         ; Data Direction for Port G Bit 0
PTGDD_PTGDD1:       equ    1                                         ; Data Direction for Port G Bit 1
PTGDD_PTGDD2:       equ    2                                         ; Data Direction for Port G Bit 2
PTGDD_PTGDD3:       equ    3                                         ; Data Direction for Port G Bit 3
PTGDD_PTGDD4:       equ    4                                         ; Data Direction for Port G Bit 4
PTGDD_PTGDD5:       equ    5                                         ; Data Direction for Port G Bit 5
PTGDD_PTGDD6:       equ    6                                         ; Data Direction for Port G Bit 6
; bit position masks
mPTGDD_PTGDD0:      equ    %00000001
mPTGDD_PTGDD1:      equ    %00000010
mPTGDD_PTGDD2:      equ    %00000100
mPTGDD_PTGDD3:      equ    %00001000
mPTGDD_PTGDD4:      equ    %00010000
mPTGDD_PTGDD5:      equ    %00100000
mPTGDD_PTGDD6:      equ    %01000000


;*** AD1SC1 - Status and Control Register; 0x00000010 ***
AD1SC1:             equ    $00000010                                ;*** AD1SC1 - Status and Control Register; 0x00000010 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1SC1_ADCH0:       equ    0                                         ; Input Channel Select Bit 0
AD1SC1_ADCH1:       equ    1                                         ; Input Channel Select Bit 1
AD1SC1_ADCH2:       equ    2                                         ; Input Channel Select Bit 2
AD1SC1_ADCH3:       equ    3                                         ; Input Channel Select Bit 3
AD1SC1_ADCH4:       equ    4                                         ; Input Channel Select Bit 4
AD1SC1_ADCO:        equ    5                                         ; Continuous Conversion Enable
AD1SC1_AIEN:        equ    6                                         ; Interrupt Enable
AD1SC1_COCO:        equ    7                                         ; Conversion Complete Flag
; bit position masks
mAD1SC1_ADCH0:      equ    %00000001
mAD1SC1_ADCH1:      equ    %00000010
mAD1SC1_ADCH2:      equ    %00000100
mAD1SC1_ADCH3:      equ    %00001000
mAD1SC1_ADCH4:      equ    %00010000
mAD1SC1_ADCO:       equ    %00100000
mAD1SC1_AIEN:       equ    %01000000
mAD1SC1_COCO:       equ    %10000000


;*** AD1SC2 - Status and Control Register 2; 0x00000011 ***
AD1SC2:             equ    $00000011                                ;*** AD1SC2 - Status and Control Register 2; 0x00000011 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1SC2_ACFGT:       equ    4                                         ; Compare Function Greater Than Enable
AD1SC2_ACFE:        equ    5                                         ; Compare Function Enable
AD1SC2_ADTRG:       equ    6                                         ; Conversion Trigger Select
AD1SC2_ADACT:       equ    7                                         ; Conversion Active
; bit position masks
mAD1SC2_ACFGT:      equ    %00010000
mAD1SC2_ACFE:       equ    %00100000
mAD1SC2_ADTRG:      equ    %01000000
mAD1SC2_ADACT:      equ    %10000000


;*** AD1R - ADC10 Result Data Right Justified; 0x00000012 ***
AD1R:               equ    $00000012                                ;*** AD1R - ADC10 Result Data Right Justified; 0x00000012 ***


;*** AD1RH - ADC10 Result Data Right Justified High; 0x00000012 ***
AD1RH:              equ    $00000012                                ;*** AD1RH - ADC10 Result Data Right Justified High; 0x00000012 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1RH_ADR8:         equ    0                                         ; ADC10 Result Data Bit 8
AD1RH_ADR9:         equ    1                                         ; ADC10 Result Data Bit 9
; bit position masks
mAD1RH_ADR8:        equ    %00000001
mAD1RH_ADR9:        equ    %00000010


;*** AD1RL - ADC10 Result Data Right Justified Low; 0x00000013 ***
AD1RL:              equ    $00000013                                ;*** AD1RL - ADC10 Result Data Right Justified Low; 0x00000013 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1RL_ADR0:         equ    0                                         ; ADC10 Result Data Bit 0
AD1RL_ADR1:         equ    1                                         ; ADC10 Result Data Bit 1
AD1RL_ADR2:         equ    2                                         ; ADC10 Result Data Bit 2
AD1RL_ADR3:         equ    3                                         ; ADC10 Result Data Bit 3
AD1RL_ADR4:         equ    4                                         ; ADC10 Result Data Bit 4
AD1RL_ADR5:         equ    5                                         ; ADC10 Result Data Bit 5
AD1RL_ADR6:         equ    6                                         ; ADC10 Result Data Bit 6
AD1RL_ADR7:         equ    7                                         ; ADC10 Result Data Bit 7
; bit position masks
mAD1RL_ADR0:        equ    %00000001
mAD1RL_ADR1:        equ    %00000010
mAD1RL_ADR2:        equ    %00000100
mAD1RL_ADR3:        equ    %00001000
mAD1RL_ADR4:        equ    %00010000
mAD1RL_ADR5:        equ    %00100000
mAD1RL_ADR6:        equ    %01000000
mAD1RL_ADR7:        equ    %10000000


;*** AD1CV - Compare Value Register; 0x00000014 ***
AD1CV:              equ    $00000014                                ;*** AD1CV - Compare Value Register; 0x00000014 ***


;*** AD1CVH - Compare Value Register High; 0x00000014 ***
AD1CVH:             equ    $00000014                                ;*** AD1CVH - Compare Value Register High; 0x00000014 ***
; bit numbers for user in BCLR, BSET, BRCLR and BRSET
AD1CVH_ADCV8:       equ    0                                         ; Compare Function Value 8
AD1CVH_ADCV9:       equ    1                                         ; Compare Function Value 9

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