📄 mc9s08el32.inc
字号:
SPIC2_SPC0: equ 0 ; SPI Pin Control 0
SPIC2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPIC2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPIC2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
mSPIC2_SPC0: equ %00000001
mSPIC2_SPISWAI: equ %00000010
mSPIC2_BIDIROE: equ %00001000
mSPIC2_MODFEN: equ %00010000
;*** SPIBR - SPI Baud Rate Register; 0x00000052 ***
SPIBR: equ $00000052 ;*** SPIBR - SPI Baud Rate Register; 0x00000052 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIBR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPIBR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPIBR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPIBR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPIBR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPIBR_SPPR2: equ 6 ; SPI Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPIBR_SPR0: equ %00000001
mSPIBR_SPR1: equ %00000010
mSPIBR_SPR2: equ %00000100
mSPIBR_SPPR0: equ %00010000
mSPIBR_SPPR1: equ %00100000
mSPIBR_SPPR2: equ %01000000
;*** SPIS - SPI Status Register; 0x00000053 ***
SPIS: equ $00000053 ;*** SPIS - SPI Status Register; 0x00000053 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIS_MODF: equ 4 ; Master Mode Fault Flag
SPIS_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPIS_SPRF: equ 7 ; SPI Read Buffer Full Flag
; bit position masks
mSPIS_MODF: equ %00010000
mSPIS_SPTEF: equ %00100000
mSPIS_SPRF: equ %10000000
;*** SPID - SPI Data Register; 0x00000055 ***
SPID: equ $00000055 ;*** SPID - SPI Data Register; 0x00000055 ***
;*** IICA - IIC Address Register; 0x00000058 ***
IICA: equ $00000058 ;*** IICA - IIC Address Register; 0x00000058 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICA_AD1: equ 1 ; Slave Address Bit 1
IICA_AD2: equ 2 ; Slave Address Bit 2
IICA_AD3: equ 3 ; Slave Address Bit 3
IICA_AD4: equ 4 ; Slave Address Bit 4
IICA_AD5: equ 5 ; Slave Address Bit 5
IICA_AD6: equ 6 ; Slave Address Bit 6
IICA_AD7: equ 7 ; Slave Address Bit 7
; bit position masks
mIICA_AD1: equ %00000010
mIICA_AD2: equ %00000100
mIICA_AD3: equ %00001000
mIICA_AD4: equ %00010000
mIICA_AD5: equ %00100000
mIICA_AD6: equ %01000000
mIICA_AD7: equ %10000000
;*** IICF - IIC Frequency Divider Register; 0x00000059 ***
IICF: equ $00000059 ;*** IICF - IIC Frequency Divider Register; 0x00000059 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICF_ICR0: equ 0 ; IIC Clock Rate Bit 0
IICF_ICR1: equ 1 ; IIC Clock Rate Bit 1
IICF_ICR2: equ 2 ; IIC Clock Rate Bit 2
IICF_ICR3: equ 3 ; IIC Clock Rate Bit 3
IICF_ICR4: equ 4 ; IIC Clock Rate Bit 4
IICF_ICR5: equ 5 ; IIC Clock Rate Bit 5
IICF_MULT0: equ 6 ; Multiplier Factor Bit 0
IICF_MULT1: equ 7 ; Multiplier Factor Bit 1
; bit position masks
mIICF_ICR0: equ %00000001
mIICF_ICR1: equ %00000010
mIICF_ICR2: equ %00000100
mIICF_ICR3: equ %00001000
mIICF_ICR4: equ %00010000
mIICF_ICR5: equ %00100000
mIICF_MULT0: equ %01000000
mIICF_MULT1: equ %10000000
;*** IICC1 - IIC Control Register 1; 0x0000005A ***
IICC1: equ $0000005A ;*** IICC1 - IIC Control Register 1; 0x0000005A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICC1_RSTA: equ 2 ; Repeat START
IICC1_TXAK: equ 3 ; Transmit Acknowledge Enable
IICC1_TX: equ 4 ; Transmit Mode Select
IICC1_MST: equ 5 ; Master Mode Select
IICC1_IICIE: equ 6 ; IIC Interrupt Enable
IICC1_IICEN: equ 7 ; IIC Enable
; bit position masks
mIICC1_RSTA: equ %00000100
mIICC1_TXAK: equ %00001000
mIICC1_TX: equ %00010000
mIICC1_MST: equ %00100000
mIICC1_IICIE: equ %01000000
mIICC1_IICEN: equ %10000000
;*** IICC - IIC Control Register; 0x0000005A ***
IICC: equ $0000005A ;*** IICC - IIC Control Register; 0x0000005A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICC_RSTA: equ 2 ; Repeat START
IICC_TXAK: equ 3 ; Transmit Acknowledge Enable
IICC_TX: equ 4 ; Transmit Mode Select
IICC_MST: equ 5 ; Master Mode Select
IICC_IICIE: equ 6 ; IIC Interrupt Enable
IICC_IICEN: equ 7 ; IIC Enable
; bit position masks
mIICC_RSTA: equ %00000100
mIICC_TXAK: equ %00001000
mIICC_TX: equ %00010000
mIICC_MST: equ %00100000
mIICC_IICIE: equ %01000000
mIICC_IICEN: equ %10000000
;*** IICS - IIC Status Register; 0x0000005B ***
IICS: equ $0000005B ;*** IICS - IIC Status Register; 0x0000005B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICS_RXAK: equ 0 ; Receive Acknowledge
IICS_IICIF: equ 1 ; IIC Interrupt Flag
IICS_SRW: equ 2 ; Slave Read/Write
IICS_ARBL: equ 4 ; Arbitration Lost
IICS_BUSY: equ 5 ; Bus Busy
IICS_IAAS: equ 6 ; Addressed as a Slave
IICS_TCF: equ 7 ; Transfer Complete Flag
; bit position masks
mIICS_RXAK: equ %00000001
mIICS_IICIF: equ %00000010
mIICS_SRW: equ %00000100
mIICS_ARBL: equ %00010000
mIICS_BUSY: equ %00100000
mIICS_IAAS: equ %01000000
mIICS_TCF: equ %10000000
;*** IICD - IIC Data I/O Register; 0x0000005C ***
IICD: equ $0000005C ;*** IICD - IIC Data I/O Register; 0x0000005C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICD_DATA0: equ 0 ; IIC Data Bit 0
IICD_DATA1: equ 1 ; IIC Data Bit 1
IICD_DATA2: equ 2 ; IIC Data Bit 2
IICD_DATA3: equ 3 ; IIC Data Bit 3
IICD_DATA4: equ 4 ; IIC Data Bit 4
IICD_DATA5: equ 5 ; IIC Data Bit 5
IICD_DATA6: equ 6 ; IIC Data Bit 6
IICD_DATA7: equ 7 ; IIC Data Bit 7
; bit position masks
mIICD_DATA0: equ %00000001
mIICD_DATA1: equ %00000010
mIICD_DATA2: equ %00000100
mIICD_DATA3: equ %00001000
mIICD_DATA4: equ %00010000
mIICD_DATA5: equ %00100000
mIICD_DATA6: equ %01000000
mIICD_DATA7: equ %10000000
;*** IICC2 - IIC Control Register 2; 0x0000005D ***
IICC2: equ $0000005D ;*** IICC2 - IIC Control Register 2; 0x0000005D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICC2_AD8: equ 0 ; Slave Address Bit 8
IICC2_AD9: equ 1 ; Slave Address Bit 9
IICC2_AD10: equ 2 ; Slave Address Bit 10
IICC2_ADEXT: equ 6 ; Address Extension
IICC2_GCAEN: equ 7 ; General Call Address Enable
; bit position masks
mIICC2_AD8: equ %00000001
mIICC2_AD9: equ %00000010
mIICC2_AD10: equ %00000100
mIICC2_ADEXT: equ %01000000
mIICC2_GCAEN: equ %10000000
;*** TPM2SC - TPM2 Status and Control Register; 0x00000060 ***
TPM2SC: equ $00000060 ;*** TPM2SC - TPM2 Status and Control Register; 0x00000060 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2SC_PS0: equ 0 ; Prescale Divisor Select Bit 0
TPM2SC_PS1: equ 1 ; Prescale Divisor Select Bit 1
TPM2SC_PS2: equ 2 ; Prescale Divisor Select Bit 2
TPM2SC_CLKSA: equ 3 ; Clock Source Select A
TPM2SC_CLKSB: equ 4 ; Clock Source Select B
TPM2SC_CPWMS: equ 5 ; Center-Aligned PWM Select
TPM2SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable
TPM2SC_TOF: equ 7 ; Timer Overflow Flag
; bit position masks
mTPM2SC_PS0: equ %00000001
mTPM2SC_PS1: equ %00000010
mTPM2SC_PS2: equ %00000100
mTPM2SC_CLKSA: equ %00001000
mTPM2SC_CLKSB: equ %00010000
mTPM2SC_CPWMS: equ %00100000
mTPM2SC_TOIE: equ %01000000
mTPM2SC_TOF: equ %10000000
;*** TPM2CNT - TPM2 Timer Counter Register; 0x00000061 ***
TPM2CNT: equ $00000061 ;*** TPM2CNT - TPM2 Timer Counter Register; 0x00000061 ***
;*** TPM2CNTH - TPM2 Timer Counter Register High; 0x00000061 ***
TPM2CNTH: equ $00000061 ;*** TPM2CNTH - TPM2 Timer Counter Register High; 0x00000061 ***
;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0x00000062 ***
TPM2CNTL: equ $00000062 ;*** TPM2CNTL - TPM2 Timer Counter Register Low; 0x00000062 ***
;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000063 ***
TPM2MOD: equ $00000063 ;*** TPM2MOD - TPM2 Timer Counter Modulo Register⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -