slfprg-s08elsl.asm

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

;*********************************************************************
; HEADER_START
;
;  	   $File Name: slfprg-s08elsl.asm$
;      Project:        Developper's HC08 Bootloader Slave
;      Description:    S08EL/SL main bootloader file
;      Platform:       HCS08
;      $Version: 9.0.6.0$
;      $Date: Mar-14-2008$ 
;      $Last Modified By: r30323$
;      Company:        Freescale Semiconductor
;      Security:       General Business
;
; =================================================================== 
; Copyright (c):      Freescale Semiconductor, 2008, All rights reserved.
;
; =================================================================== 
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END

; labels SIZE, FAMILY and IRQOPTION defined externally:
; SIZE = 8, 16, 32 depending whether what memory size of EL/SL family is required
; FAMILY = 0 EL family, FAMILY = 1 SL family
; 
; IRQOPTION *NOT* defined >> regular version
; IRQOPTION defined >> regular version using IRQ option (bootloading won't start if IRQ high)
;
; label HISPEED => if defined, 38400Bd is used instead of 9600Bd

	include "mc9s08el32.inc"

;!!!;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;!!!
;!!!   This S08EL/SL bootloader requires hc08sprg.exe of version 9.0.37.0 or higher
;!!!
;!!!;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


RCS_ENA    	EQU     1     	; READ COMMAND SUPPORTED?

  IF RCS_ENA = 1
RCS         EQU     $80   	; READ COMMAND SUPPORTED
  ELSE
RCS         EQU     0     	; READ COMMAND unSUPPORTED
  ENDIF

VER_NUM     EQU     $06   	; FC protocol version number (S08 long)

IDENTS      MACRO

          IF FAMILY = 0  ; EL
			      DC.B	'EL'
          ENDIF

          IF FAMILY = 1  ; SL
			      DC.B	'SL'
          ENDIF

          IF SIZE = 32
            DC.B     '32'   ; 32kb string
          ENDIF
          IF SIZE = 16
            DC.B     '16'   ; 16kb string
          ENDIF
          IF SIZE = 8
            DC.B     '8'    ; 8kb string
          ENDIF

          IFDEF IRQOPTION
            DC.B     '-irq'     ; IRQ option used
          ENDIF

            DC.B    0
            ENDM

ERBLK_LEN	EQU		512
WRBLK_LEN	EQU		64      

ADDR24  MACRO
          DC.B  (\1) / $10000
          DC.W  (\1) & $0FFFF
        ENDM


          IF SIZE = 32
FLS_BEG		EQU		$8000   ; FLASH #0 block start
		  ENDIF

          IF SIZE = 16
FLS_BEG		EQU		$C000   ; FLASH #0 block start
		  ENDIF

          IF SIZE = 8
FLS_BEG		EQU		$E000   ; FLASH #0 block start
		  ENDIF

          IF FAMILY = 0  ; EL
EEP_BEG   EQU   $1700   ; EEPROM page 0 start
          ENDIF

          IF FAMILY = 1  ; SL
EEP_BEG   EQU   $1780   ; EEPROM page 0 start
          ENDIF

EEP_END   EQU   $1800   ; EEPROM page 0 end
                        ; EEPROM page 1 is $10000 higher
   
FLS_END		EQU		$FBC0   ; FLASH #0 block end
REL_VECT	EQU 	$FBC0	  ; newly relocated int. vectors


INT_VECT	EQU		$FFC0	  ; start of table of original vectors!


F_ICSTRM    equ   $FFAF
F_ICSFTRM   equ   $FFAE

			XDEF	main
;*******************************************************************************************
  
WR_DATA		EQU	    'W'
RD_DATA		EQU	    'R'
ENDPRG		EQU	    'Q'
ERASE	  	EQU	    'E'
ACK		    EQU	    $FC
IDENT		  EQU	    'I'

T100MS		EQU	    255

ILOP        MACRO
            DC.B    $8d             ; this is illegal operation code
            ENDM
;*******************************************************************************************
MY_ZEROPAGE:	SECTION  SHORT

ADRH: 	DS.B	1
ADRS: 	DS.W	1
ADRR: 	DS.W	1
LEN:  	DS.B	1
STAT: 	DS.B	1
STACK:	DS.W	1

DEFAULT_RAM:    SECTION

DATA:	  DS.B	WRBLK_LEN

;*******************************************************************************************
DEFAULT_ROM:	SECTION
     
ID_STRING:
		    DC.B	3				    ; number of memory blocks
        ADDR24	FLS_BEG     ; START ADDRESS OF FLASH	
        ADDR24  FLS_END		  ; END ADDRESS OF FLASH																						    
        ADDR24	EEP_BEG     ; START ADDRESS OF EEP0	
        ADDR24  EEP_END		  ; END ADDRESS OF EEP0																						    
        ADDR24	EEP_BEG + $10000    ; START ADDRESS OF EEP1	
        ADDR24  EEP_END + $10000		  ; END ADDRESS OF EEP1																						    
		    DC.W	REL_VECT		; POINTER TO APPLICATION VECTOR TABLE
        DC.W	INT_VECT		; POINTER TO BEGINING OF FLASH INT. VECTORS
        DC.W	ERBLK_LEN		; ERASE BLCK LENGTH OF FLASH ALG.
        DC.W	WRBLK_LEN		; WRITE BLCK LENGTH OF FLASH ALG.

		IDENTS
ID_STRING_END:

    	XDEF 	MY_NVPROT	
    	XDEF	MY_NVOPT 	

;*******************************************************************************************
NVPROT_ROM:		SECTION
MY_NVPROT	  DC.B	%11111101	; flash protected (from 0xFC00), EEPROM unprotected 

NVOPT_ROM:		SECTION
MY_NVOPT	  DC.B	%10100010	; backdoor enable, redirection enable, (un)secured flash [last 10], EEPROM 8 byte page

DEFAULT_ROM:	SECTION
;*******************************************************************************************
main:
    IFDEF IRQOPTION
        BIH     PVEC0                   ; if IRQ high, jump directly to real app.
    ENDIF
        LDA     SRS                     ; fetch RESET status reg.
        TSTA                            ; check if zero (this happens if RESET pulse is too short)
        BEQ     slfprg                  ; if so, jump to self programming                
        AND     #%10000000              ; mask only POR RESET source      
        BNE     slfprg                  ; any of these sources, go to self programming
PVEC0:  		
    		LDHX	  #(REL_VECT|$00FF)&$FFFE	; there should be relocated reset vector of the new app.
    		LDA		  ,X
    		PSHA
    		AND	  	1,X
    		LDX	  	1,X
    		PULH
    		INCA
    		BEQ	  	slfprg					  ; don't jump if empty vector!
        JMP     ,X					  	  ; jump to relocated application!

slfprg:        
        LDA     F_ICSTRM
        STA     ICSTRM

        LDA     F_ICSFTRM
        ORA     ICSSC
        STA     ICSSC

    		LDA	  	#%00000010
    		STA	  	SOPT1				      ; COP disable, BDM enable (for now)

        MOV	  	#%01000000,ICSC2	; bus divide :2, ie bus = 8MHz

  			; f(BUS)=f(ICGOUT)/2
	  
    		LDA	  	FSTAT
    		ORA		  #mFSTAT_FACCERR				                
    		STA	  	FSTAT					    ; clear any FACCERR flag

        LDA	  	#(mFCDIV_PRDIV8 + 4) ; div by 8*(4+1) to fit into 150-200kHz Flash clock!
        STA		  FCDIV
        
        MOV     #%00001100,SCIC2  ; transmit & receive enable
    		CLR	  	SCIBDH

	  IFNDEF HISPEED
    		MOV	  	#52, SCIBDL			  ; BUS (8.0M)/(16 * 52) = 9600Bd
	  ELSE
    		MOV	  	#13, SCIBDL				; BUS (8.0M)/(16 * 4) = 38400Bd
	  ENDIF
      	CLR     SCIC3

; OPTIONAL DELAY - if your RS232 hardware is lazy, uncomment following delay

;        CLRX
;DLY2:   CLRA
;DLY1:   NOP
;