📄 mc9s08sh8.inc
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mSCIS2_LBKDIF: equ %10000000
;*** SCIC3 - SCI Control Register 3; 0x0000003E ***
SCIC3: equ $0000003E ;*** SCIC3 - SCI Control Register 3; 0x0000003E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC3_PEIE: equ 0 ; Parity Error Interrupt Enable
SCIC3_FEIE: equ 1 ; Framing Error Interrupt Enable
SCIC3_NEIE: equ 2 ; Noise Error Interrupt Enable
SCIC3_ORIE: equ 3 ; Overrun Interrupt Enable
SCIC3_TXINV: equ 4 ; Transmit Data Inversion
SCIC3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode
SCIC3_T8: equ 6 ; Ninth Data Bit for Transmitter
SCIC3_R8: equ 7 ; Ninth Data Bit for Receiver
; bit position masks
mSCIC3_PEIE: equ %00000001
mSCIC3_FEIE: equ %00000010
mSCIC3_NEIE: equ %00000100
mSCIC3_ORIE: equ %00001000
mSCIC3_TXINV: equ %00010000
mSCIC3_TXDIR: equ %00100000
mSCIC3_T8: equ %01000000
mSCIC3_R8: equ %10000000
;*** SCID - SCI Data Register; 0x0000003F ***
SCID: equ $0000003F ;*** SCID - SCI Data Register; 0x0000003F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCID_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCID_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCID_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCID_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCID_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCID_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCID_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCID_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCID_R0_T0: equ %00000001
mSCID_R1_T1: equ %00000010
mSCID_R2_T2: equ %00000100
mSCID_R3_T3: equ %00001000
mSCID_R4_T4: equ %00010000
mSCID_R5_T5: equ %00100000
mSCID_R6_T6: equ %01000000
mSCID_R7_T7: equ %10000000
;*** ICSC1 - ICS Control Register 1; 0x00000048 ***
ICSC1: equ $00000048 ;*** ICSC1 - ICS Control Register 1; 0x00000048 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC1_IREFSTEN: equ 0 ; Internal Reference Stop Enable
ICSC1_IRCLKEN: equ 1 ; Internal Reference Clock Enable
ICSC1_IREFS: equ 2 ; Internal Reference Select
ICSC1_RDIV0: equ 3 ; Reference Divider, bit 0
ICSC1_RDIV1: equ 4 ; Reference Divider, bit 1
ICSC1_RDIV2: equ 5 ; Reference Divider, bit 2
ICSC1_CLKS0: equ 6 ; Clock Source Select, bit 0
ICSC1_CLKS1: equ 7 ; Clock Source Select, bit 1
; bit position masks
mICSC1_IREFSTEN: equ %00000001
mICSC1_IRCLKEN: equ %00000010
mICSC1_IREFS: equ %00000100
mICSC1_RDIV0: equ %00001000
mICSC1_RDIV1: equ %00010000
mICSC1_RDIV2: equ %00100000
mICSC1_CLKS0: equ %01000000
mICSC1_CLKS1: equ %10000000
;*** ICSC2 - ICS Control Register 2; 0x00000049 ***
ICSC2: equ $00000049 ;*** ICSC2 - ICS Control Register 2; 0x00000049 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC2_EREFSTEN: equ 0 ; External Reference Stop Enable
ICSC2_ERCLKEN: equ 1 ; External Reference Enable
ICSC2_EREFS: equ 2 ; External Reference Select
ICSC2_LP: equ 3 ; Low Power Select
ICSC2_HGO: equ 4 ; High Gain Oscillator Select
ICSC2_RANGE: equ 5 ; Frequency Range Select
ICSC2_BDIV0: equ 6 ; Bus Frequency Divider, bit 0
ICSC2_BDIV1: equ 7 ; Bus Frequency Divider, bit 1
; bit position masks
mICSC2_EREFSTEN: equ %00000001
mICSC2_ERCLKEN: equ %00000010
mICSC2_EREFS: equ %00000100
mICSC2_LP: equ %00001000
mICSC2_HGO: equ %00010000
mICSC2_RANGE: equ %00100000
mICSC2_BDIV0: equ %01000000
mICSC2_BDIV1: equ %10000000
;*** ICSTRM - ICS Trim Register; 0x0000004A ***
ICSTRM: equ $0000004A ;*** ICSTRM - ICS Trim Register; 0x0000004A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSTRM_TRIM0: equ 0 ; ICS Trim Setting, bit 0
ICSTRM_TRIM1: equ 1 ; ICS Trim Setting, bit 1
ICSTRM_TRIM2: equ 2 ; ICS Trim Setting, bit 2
ICSTRM_TRIM3: equ 3 ; ICS Trim Setting, bit 3
ICSTRM_TRIM4: equ 4 ; ICS Trim Setting, bit 4
ICSTRM_TRIM5: equ 5 ; ICS Trim Setting, bit 5
ICSTRM_TRIM6: equ 6 ; ICS Trim Setting, bit 6
ICSTRM_TRIM7: equ 7 ; ICS Trim Setting, bit 7
; bit position masks
mICSTRM_TRIM0: equ %00000001
mICSTRM_TRIM1: equ %00000010
mICSTRM_TRIM2: equ %00000100
mICSTRM_TRIM3: equ %00001000
mICSTRM_TRIM4: equ %00010000
mICSTRM_TRIM5: equ %00100000
mICSTRM_TRIM6: equ %01000000
mICSTRM_TRIM7: equ %10000000
;*** ICSSC - ICS Status and Control Register; 0x0000004B ***
ICSSC: equ $0000004B ;*** ICSSC - ICS Status and Control Register; 0x0000004B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSSC_FTRIM: equ 0 ; ICS Fine Trim
ICSSC_OSCINIT: equ 1 ; OSC Initialization
ICSSC_CLKST0: equ 2 ; Clock Mode Status, bit 0
ICSSC_CLKST1: equ 3 ; Clock Mode Status, bit 1
ICSSC_IREFST: equ 4 ; Internal Reference Status
; bit position masks
mICSSC_FTRIM: equ %00000001
mICSSC_OSCINIT: equ %00000010
mICSSC_CLKST0: equ %00000100
mICSSC_CLKST1: equ %00001000
mICSSC_IREFST: equ %00010000
;*** SPIC1 - SPI Control Register 1; 0x00000050 ***
SPIC1: equ $00000050 ;*** SPIC1 - SPI Control Register 1; 0x00000050 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIC1_LSBFE: equ 0 ; LSB First (Shifter Direction)
SPIC1_SSOE: equ 1 ; Slave Select Output Enable
SPIC1_CPHA: equ 2 ; Clock Phase
SPIC1_CPOL: equ 3 ; Clock Polarity
SPIC1_MSTR: equ 4 ; Master/Slave Mode Select
SPIC1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable
SPIC1_SPE: equ 6 ; SPI System Enable
SPIC1_SPIE: equ 7 ; SPI Interrupt Enable (for SPRF and MODF)
; bit position masks
mSPIC1_LSBFE: equ %00000001
mSPIC1_SSOE: equ %00000010
mSPIC1_CPHA: equ %00000100
mSPIC1_CPOL: equ %00001000
mSPIC1_MSTR: equ %00010000
mSPIC1_SPTIE: equ %00100000
mSPIC1_SPE: equ %01000000
mSPIC1_SPIE: equ %10000000
;*** SPIC2 - SPI Control Register 2; 0x00000051 ***
SPIC2: equ $00000051 ;*** SPIC2 - SPI Control Register 2; 0x00000051 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIC2_SPC0: equ 0 ; SPI Pin Control 0
SPIC2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPIC2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPIC2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
mSPIC2_SPC0: equ %00000001
mSPIC2_SPISWAI: equ %00000010
mSPIC2_BIDIROE: equ %00001000
mSPIC2_MODFEN: equ %00010000
;*** SPIBR - SPI Baud Rate Register; 0x00000052 ***
SPIBR: equ $00000052 ;*** SPIBR - SPI Baud Rate Register; 0x00000052 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIBR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPIBR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPIBR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPIBR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPIBR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPIBR_SPPR2: equ 6 ; SPI Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPIBR_SPR0: equ %00000001
mSPIBR_SPR1: equ %00000010
mSPIBR_SPR2: equ %00000100
mSPIBR_SPPR0: equ %00010000
mSPIBR_SPPR1: equ %00100000
mSPIBR_SPPR2: equ %01000000
;*** SPIS - SPI Status Register; 0x00000053 ***
SPIS: equ $00000053 ;*** SPIS - SPI Status Register; 0x00000053 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIS_MODF: equ 4 ; Master Mode Fault Flag
SPIS_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPIS_SPRF: equ 7 ; SPI Read Buffer Full Flag
; bit position masks
mSPIS_MODF: equ %00010000
mSPIS_SPTEF: equ %00100000
mSPIS_SPRF: equ %10000000
;*** SPID - SPI Data Register; 0x00000055 ***
SPID: equ $00000055 ;*** SPID - SPI Data Register; 0x00000055 ***
;*** IICA - IIC Address Register; 0x00000058 ***
IICA: equ $00000058 ;*** IICA - IIC Address Register; 0x00000058 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICA_AD1: equ 1 ; Slave Address Bit 1
IICA_AD2: equ 2 ; Slave Address Bit 2
IICA_AD3: equ 3 ; Slave Address Bit 3
IICA_AD4: equ 4 ; Slave Address Bit 4
IICA_AD5: equ 5 ; Slave Address Bit 5
IICA_AD6: equ 6 ; Slave Address Bit 6
IICA_AD7: equ 7 ; Slave Address Bit 7
; bit position masks
mIICA_AD1: equ %00000010
mIICA_AD2: equ %00000100
mIICA_AD3: equ %00001000
mIICA_AD4: equ %00010000
mIICA_AD5: equ %00100000
mIICA_AD6: equ %01000000
mIICA_AD7: equ %10000000
;*** IICF - IIC Frequency Divider Register; 0x00000059 ***
IICF: equ $00000059 ;*** IICF - IIC Frequency Divider Register; 0x00000059 ***
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