📄 mc9s08sh8.inc
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; Based on CPU DB MC9S08SH8_20, version 3.00.011 (RegistersPrg V2.18)
; ###################################################################
; Filename : mc9s08sh8.inc
; Processor : MC9S08SH8_20
; FileFormat: V2.18
; DataSheet : MC9S08SH8 Rev. 0.04 5/24/2006
; Compiler : CodeWarrior compiler
; Date/Time : 25.7.2007, 8:45
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 19.07.2007, V2.18 :
; - Improved number of blanked lines inside register structures
;
; CPU Registers Revisions:
; - none
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $0000E000
ROMEnd: equ $0000FFAD
Z_RAMStart: equ $00000080
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $0000027F
;
VReserved31: equ $0000FFC0
Vacmp: equ $0000FFC2
VReserved29: equ $0000FFC4
VReserved28: equ $0000FFC6
VReserved27: equ $0000FFC8
Vmtim: equ $0000FFCA
Vrtc: equ $0000FFCC
Viic: equ $0000FFCE
Vadc: equ $0000FFD0
VReserved22: equ $0000FFD2
Vportb: equ $0000FFD4
Vporta: equ $0000FFD6
VReserved19: equ $0000FFD8
Vscitx: equ $0000FFDA
Vscirx: equ $0000FFDC
Vscierr: equ $0000FFDE
Vspi: equ $0000FFE0
Vtpm2ovf: equ $0000FFE2
Vtpm2ch1: equ $0000FFE4
Vtpm2ch0: equ $0000FFE6
Vtpm1ovf: equ $0000FFE8
VReserved10: equ $0000FFEA
VReserved9: equ $0000FFEC
VReserved8: equ $0000FFEE
VReserved7: equ $0000FFF0
Vtpm1ch1: equ $0000FFF2
Vtpm1ch0: equ $0000FFF4
VReserved4: equ $0000FFF6
Vlvd: equ $0000FFF8
Virq: equ $0000FFFA
Vswi: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PTAD - Port A Data Register; 0x00000000 ***
PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0
PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1
PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2
PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3
PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4
PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5
; bit position masks
mPTAD_PTAD0: equ %00000001
mPTAD_PTAD1: equ %00000010
mPTAD_PTAD2: equ %00000100
mPTAD_PTAD3: equ %00001000
mPTAD_PTAD4: equ %00010000
mPTAD_PTAD5: equ %00100000
;*** PTADD - Port A Data Direction Register; 0x00000001 ***
PTADD: equ $00000001 ;*** PTADD - Port A Data Direction Register; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0
PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1
PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2
PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3
PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4
PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5
; bit position masks
mPTADD_PTADD0: equ %00000001
mPTADD_PTADD1: equ %00000010
mPTADD_PTADD2: equ %00000100
mPTADD_PTADD3: equ %00001000
mPTADD_PTADD4: equ %00010000
mPTADD_PTADD5: equ %00100000
;*** PTBD - Port B Data Register; 0x00000002 ***
PTBD: equ $00000002 ;*** PTBD - Port B Data Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBD_PTBD0: equ 0 ; Port B Data Register Bit 0
PTBD_PTBD1: equ 1 ; Port B Data Register Bit 1
PTBD_PTBD2: equ 2 ; Port B Data Register Bit 2
PTBD_PTBD3: equ 3 ; Port B Data Register Bit 3
PTBD_PTBD4: equ 4 ; Port B Data Register Bit 4
PTBD_PTBD5: equ 5 ; Port B Data Register Bit 5
PTBD_PTBD6: equ 6 ; Port B Data Register Bit 6
PTBD_PTBD7: equ 7 ; Port B Data Register Bit 7
; bit position masks
mPTBD_PTBD0: equ %00000001
mPTBD_PTBD1: equ %00000010
mPTBD_PTBD2: equ %00000100
mPTBD_PTBD3: equ %00001000
mPTBD_PTBD4: equ %00010000
mPTBD_PTBD5: equ %00100000
mPTBD_PTBD6: equ %01000000
mPTBD_PTBD7: equ %10000000
;*** PTBDD - Port B Data Direction Register; 0x00000003 ***
PTBDD: equ $00000003 ;*** PTBDD - Port B Data Direction Register; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBDD_PTBDD0: equ 0 ; Data Direction for Port B Bit 0
PTBDD_PTBDD1: equ 1 ; Data Direction for Port B Bit 1
PTBDD_PTBDD2: equ 2 ; Data Direction for Port B Bit 2
PTBDD_PTBDD3: equ 3 ; Data Direction for Port B Bit 3
PTBDD_PTBDD4: equ 4 ; Data Direction for Port B Bit 4
PTBDD_PTBDD5: equ 5 ; Data Direction for Port B Bit 5
PTBDD_PTBDD6: equ 6 ; Data Direction for Port B Bit 6
PTBDD_PTBDD7: equ 7 ; Data Direction for Port B Bit 7
; bit position masks
mPTBDD_PTBDD0: equ %00000001
mPTBDD_PTBDD1: equ %00000010
mPTBDD_PTBDD2: equ %00000100
mPTBDD_PTBDD3: equ %00001000
mPTBDD_PTBDD4: equ %00010000
mPTBDD_PTBDD5: equ %00100000
mPTBDD_PTBDD6: equ %01000000
mPTBDD_PTBDD7: equ %10000000
;*** PTCD - Port C Data Register; 0x00000004 ***
PTCD: equ $00000004 ;*** PTCD - Port C Data Register; 0x00000004 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTCD_PTCD0: equ 0 ; Port C Data Register Bit 0
PTCD_PTCD1: equ 1 ; Port C Data Register Bit 1
PTCD_PTCD2: equ 2 ; Port C Data Register Bit 2
PTCD_PTCD3: equ 3 ; Port C Data Register Bit 3
; bit position masks
mPTCD_PTCD0: equ %00000001
mPTCD_PTCD1: equ %00000010
mPTCD_PTCD2: equ %00000100
mPTCD_PTCD3: equ %00001000
;*** PTCDD - Port C Data Direction Register; 0x00000005 ***
PTCDD: equ $00000005 ;*** PTCDD - Port C Data Direction Register; 0x00000005 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTCDD_PTCDD0: equ 0 ; Data Direction for Port C Bit 0
PTCDD_PTCDD1: equ 1 ; Data Direction for Port C Bit 1
PTCDD_PTCDD2: equ 2 ; Data Direction for Port C Bit 2
PTCDD_PTCDD3: equ 3 ; Data Direction for Port C Bit 3
; bit position masks
mPTCDD_PTCDD0: equ %00000001
mPTCDD_PTCDD1: equ %00000010
mPTCDD_PTCDD2: equ %00000100
mPTCDD_PTCDD3: equ %00001000
;*** ACMPSC - ACMP Status and Control Register; 0x0000000E ***
ACMPSC: equ $0000000E ;*** ACMPSC - ACMP Status and Control Register; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMPSC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMPSC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMPSC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMPSC_ACO: equ 3 ; Analog Comparator Output
ACMPSC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMPSC_ACF: equ 5 ; Analog Comparator Flag
ACMPSC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMPSC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMPSC_ACMOD0: equ %00000001
mACMPSC_ACMOD1: equ %00000010
mACMPSC_ACOPE: equ %00000100
mACMPSC_ACO: equ %00001000
mACMPSC_ACIE: equ %00010000
mACMPSC_ACF: equ %00100000
mACMPSC_ACBGS: equ %01000000
mACMPSC_ACME: equ %10000000
;*** ADCSC1 - Status and Control Register 1; 0x00000010 ***
ADCSC1: equ $00000010 ;*** ADCSC1 - Status and Control Register 1; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCSC1_ADCH0: equ 0 ; Input Channel Select Bit 0
ADCSC1_ADCH1: equ 1 ; Input Channel Select Bit 1
ADCSC1_ADCH2: equ 2 ; Input Channel Select Bit 2
ADCSC1_ADCH3: equ 3 ; Input Channel Select Bit 3
ADCSC1_ADCH4: equ 4 ; Input Channel Select Bit 4
ADCSC1_ADCO: equ 5 ; Continuous Conversion Enable - ADCO is used to enable continuous conversions
ADCSC1_AIEN: equ 6 ; Interrupt Enable - AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted
ADCSC1_COCO: equ 7 ; Conversion Complete Flag - The COCO flag is a read-only bit which is set each time a conversion is completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE = 1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared whenever ADCSC1 is written or whenever ADCRL is read
; bit position masks
mADCSC1_ADCH0: equ %00000001
mADCSC1_ADCH1: equ %00000010
mADCSC1_ADCH2: equ %00000100
mADCSC1_ADCH3: equ %00001000
mADCSC1_ADCH4: equ %00010000
mADCSC1_ADCO: equ %00100000
mADCSC1_AIEN: equ %01000000
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