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📄 slfprg-s08qe.asm

📁 M68HC08及HCS08系列单片机bootloader引导程序源码/示例
💻 ASM
📖 第 1 页 / 共 2 页
字号:
VEC21:  JMP     main            ; vector 21
VEC22:  JMP     main            ; vector 22
VEC23:  JMP     main            ; vector 23
VEC24:  JMP     main            ; vector 24
VEC25:  JMP     main            ; vector 25
VEC26:  JMP     main            ; vector 26
VEC27:  JMP     main            ; vector 27
VEC28:  JMP     main            ; vector 28
VEC29:  JMP     main            ; vector 29
VEC30:  JMP     main            ; vector 30
VEC31:  JMP     main            ; vector 31
  
;*******************************************************************************************
NVPROT_ROM:		SECTION
MY_NVPROT	  DC.B	%11111101 ; flash protected (from 0xFC00), this is a smallest block on QE

NVOPT_ROM:		SECTION
MY_NVOPT	  DC.B	%10000010	; backdoor enable, (un)secured flash [last 10]

DEFAULT_ROM:	SECTION
;*******************************************************************************************
main:
    IFDEF IRQOPTION
        BIH     PVEC0                   ; if IRQ high, jump directly to real app.
    ENDIF
        LDA     SRS                     ; fetch RESET status reg.
        TSTA                            ; check if zero (this happens if RESET pulse is too short)
        BEQ     slfprg                  ; if so, jump to self programming                
        AND     #%11000000              ; mask only POR and PIN RESET source      
        BNE     slfprg                  ; any of these sources, go to self programming
PVEC0:  JMP     VEC0						        ; jump to relocated application!

slfprg:        
    		LDA	  	#%00000010
    		STA	  	SOPT1					    ; COP disable, BDM enable (for now)
        MOV	  	#%00000100,ICSC1	; FEI mode, IREFS = 1

        MOV	  	#%00000000,ICSSC	; DRS=0 (16-20MHz DCO range)
        MOV	  	#%00000000,ICSC2	; BDIV=00 (/1), 16-20MHz, reqd' 16MHz, bus = ICS/2
        
    		LDA		  FSTAT
    		ORA	  	#mFSTAT_FACCERR
    		STA	  	FSTAT					    ; clear any FACCERR flag

        LDA	  	#39       		    ; div by 40 to fit into 150-200kHz Flash clock!
        STA		  FCDIV
        
        LDA     #%00001100
        STA     SCC2        	    ; transmit & receive enable
    		CLRA
    		STA	  	SCIBDH

	  IFNDEF HISPEED
    		LDA	  	#52
    		STA     SCIBDL				    ; BUS (8M)/(16 * 52) = 9600Bd
	  ELSE
    		LDA	  	#13
    		STA     SCIBDL				    ; BUS (8M)/(16 * 13) = 38400Bd
	  ENDIF
      	CLRA
      	STA     SCC3

      	LDA	    SCS1
      	LDA	    #ACK
      	STA     SCDR

      	LDX	    #T100MS
L2:	    CLRA
L1:	    PSHA
        LDA     SCS1
        AND     #mRDRF
        BNE     CAUGHT
      	PULA
      	DBNZA	  L1
      	DBNZX	  L2

ILOP:
;       timeout
        ILOP          ; generate RESET by doing illegal operation
;*******************************************************************************************
CAUGHT:			; CAUGHT IN SELF-PROGRAMMING?
      	BSR     READ

;*******************************************************************************************
; successful return from all write routines
SUCC:
        LDA     #ACK
      	BSR     WRITE

;fall thru to background
;*******************************************************************************************
; BEGIN OF BACKGROUND COMMAND LOOP
BCKGND:
      	BSR     READ
            
        CBEQA   #ERASE, ERASE_COM       ; Erase command
        CBEQA   #WR_DATA, WR_DATA_COM   ; Write (program) command
        CBEQA   #IDENT, IDENT_COM       ; Ident command
      IF RCS_ENA = 1
        CBEQA   #RD_DATA, RD_DATA_COM   ; Read command
      ENDIF

        ; if no valid command found (including Quit)
        ; generate reset too!
        ILOP          ; generate RESET by doing illegal operation
        
;*******************************************************************************************
IDENT_COM:                        ; TRANSFER OF IDENTIFICATION STRING
        LDA     #(VER_NUM | RCS)  ; version number & "Read command supported" flag
    		BSR	  	WRITE
    		LDA	  	SDIDH			        ; system device identification 1 register (high)
    		BSR	  	WRITE
    		LDA	  	SDIDL			        ; system device identification 1 register (low)
    		BSR	  	WRITE

        MOV     #ID_STRING_END-ID_STRING, LEN
    		LDHX  	#ID_STRING
        BSR     WRITE_LOOP
                 
        BRA     BCKGND            ; finish without ACK
;*******************************************************************************************
WRITE_LOOP:             ; start address in HX, length in LEN
      	LDA	    ,X
        BSR	    WRITE
      	AIX	    #1
        DBNZ    LEN, WRITE_LOOP
        RTS
;*******************************************************************************************
      IF RCS_ENA = 1
RD_DATA_COM:
      	BSR     READ
        STA     PPAGE
      	BSR     READ
      	STA	    ADRS
      	BSR     READ
      	STA	    ADRS+1
      	BSR     READ
      	STA	    LEN
      	LDHX  	ADRS
        
        BSR     WRITE_LOOP

        BRA     BCKGND            ; finish without ACK
      ENDIF

;*******************************************************************************************
WRITE:	
        PSHA
WRITE1:
        LDA     SCS1
        AND     #mTC
        BEQ     WRITE1
        PULA
      	STA	    SCDR
      	RTS

READ:
        LDA     SCS1
        AND     #mRDRF
        BEQ     READ

      	LDA	    SCDR
      	RTS

;*******************************************************************************************
ERASE_COM:
      	BSR     READ
        STA     PPAGE
      	BSR     READ
      	STA	    ADRS
      	BSR     READ
      	STA	    ADRS+1

    		lda   	#(mFSTAT_FPVIOL+mFSTAT_FACCERR) ;mask
    		sta   	FSTAT 				      ;abort any command and clear errors

    		mov		  #EraseSubSize, STAT	;length of flash erase routine to STAT
    		tsx
    		sthx  	STACK
    		ldhx  	#EraseSubEnd-1 		  ;point at last byte to move to stack

    		bra   	DoOnStack 			    ;execute prog code from stack RAM
;*******************************************************************************************
WR_DATA_COM:
      	BSR     READ
        STA     PPAGE
      	BSR     READ
      	STA	    ADRS
      	BSR     READ
      	STA	    ADRS+1
      	BSR     READ
      	STA	    STAT
        STA     LEN
        LDHX    #DATA
        STHX  	ADRR
WR_DATA_L1:
      	BSR     READ
        STA     ,X
        AIX     #1
        DBNZ    STAT,WR_DATA_L1
		
    		lda   	#(mFSTAT_FPVIOL+mFSTAT_FACCERR) ;mask
    		sta   	FSTAT 				      ;abort any command and clear errors

    		mov		  #ProgSubSize, STAT	;length of flash prog routine to STAT
    		tsx
    		sthx  	STACK
    		ldhx 	  #ProgSubEnd-1		    ;point at last byte to move to stack

;		bra 	DoOnStack 			;execute prog code from stack RAM
		; fallthru to DoOnStack
;*******************************************************************************************
DoOnStack: 
    		lda   	,x 				  ;read from flash
    		psha 					      ;move onto stack
    		aix 	  #-1 			  ;next byte to move
    		dbnz  	STAT, DoOnStack
    		tsx 					      ;point to sub on stack
    		jmp 	  ,x 				  ;execute the sub on the stack (will return on it's own)		
;*******************************************************************************************
EraseSub: 	
    		ldhx  	ADRS		 	  ;get flash address
    		sta   	0,x 			  ;write to flash; latch addr and data
    		lda   	#mPageErase ;get flash command
    		sta   	FCMD 			  ;write the flash command
    		lda   	#mFSTAT_FCBEF 		;mask to initiate command
    		sta   	FSTAT 			;[pwpp] register command
    		nop 					      ;[p] want min 4~ from w cycle to r
ChkDoneErase: 
    		lda   	FSTAT 			;[prpp] so FCCF is valid
    		lsla 					      ;FCCF now in MSB
    		bpl   	ChkDoneErase 	;loop if FCCF = 0

    		ldhx    STACK
    		txs
        jmp     SUCC		    ;refer status back to PC
EraseSubEnd: 
EraseSubSize: equ (*-EraseSub)
;*******************************************************************************************
ProgSub: 	
    		lda   	FSTAT 			;check FCBEF
    		and   	#mFSTAT_FCBEF 		;mask it
    		beq	  	ProgSub			;loop if not empty
    		
    		ldhx  	ADRR
    		lda	  	0,x
    		aix	  	#1
    		sthx  	ADRR
    		
    		ldhx  	ADRS		 	  ;get flash address
    		sta   	0,x 			  ;write to flash; latch addr and data
    		aix	  	#1
    		sthx  	ADRS
    		
    		lda   	#mBurstProg ;get flash command
    		sta   	FCMD 			  ;write the flash command
    		lda   	#mFSTAT_FCBEF 		;mask to initiate command
    		sta   	FSTAT 			;[pwpp] register command
    		dbnz  	LEN,ProgSub	;all bytes in a row?
ChkDoneProg: 
    		lda   	FSTAT 			;[prpp] so FCCF is valid
    		lsla 					      ;FCCF now in MSB
    		bpl   	ChkDoneProg 	;loop if FCCF = 0
    		
    		ldhx	  STACK
    		txs
        jmp     SUCC	    	;refer status back to PC
ProgSubEnd: 
ProgSubSize: equ (*-ProgSub)
;*******************************************************************************************
END            

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