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📄 slfprg-s08qe.asm

📁 M68HC08及HCS08系列单片机bootloader引导程序源码/示例
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;*********************************************************************
; HEADER_START
;
;  	   $File Name: slfprg-s08qe.asm$
;      Project:        Developper's HC08 Bootloader Slave
;      Description:    S08QE main bootloader file
;      Platform:       HCS08
;      $Version: 9.0.4.0$
;      $Date: Mar-14-2008$ 
;      $Last Modified By: r30323$
;      Company:        Freescale Semiconductor
;      Security:       General Business
;
; =================================================================== 
; Copyright (c):      Freescale Semiconductor, 2007, All rights reserved.
;
; =================================================================== 
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END

; labels SIZE and IRQOPTION defined externally:
; SIZE = 64, 96, 128 depending whether what memory size of QE family is required
; 
; IRQOPTION *NOT* defined >> regular version
; IRQOPTION defined >> regular version using IRQ option (bootloading won't start if IRQ high)
;
; label HISPEED => if defined, 38400Bd is used instead of 9600Bd

	include "mc9s08qe128.inc"


RCS_ENA    	EQU     1     	; READ COMMAND SUPPORTED?


	IFNDEF SCI
SCI		EQU		1
	ENDIF	

	IF SCI = 1
SCIBDH	equ SCI1BDH
SCIBDL	equ SCI1BDL
SCC1  	equ SCI1C1
SCC2  	equ SCI1C2
SCC3  	equ SCI1C3
SCS1  	equ SCI1S1
SCS2  	equ SCI1S2
SCDR  	equ SCI1D
	ENDIF

	IF SCI = 2
SCIBDH	equ SCI2BDH
SCIBDL	equ SCI2BDL
SCC1  	equ SCI2C1
SCC2  	equ SCI2C2
SCC3  	equ SCI2C3
SCS1  	equ SCI2S1
SCS2  	equ SCI2S2
SCDR  	equ SCI2D
	ENDIF

; bit numbers for use in BCLR, BSET, BRCLR, and BRSET
TDRE:       equ   7           ;(bit #7) Tx data register empty
TC:         equ   6           ;(bit #6) transmit complete
RDRF:       equ   5           ;(bit #5) Rx data register full
IDLE:       equ   4           ;(bit #4) idle line detected
OR:         equ   3           ;(bit #3) Rx over run
NF:         equ   2           ;(bit #2) Rx noise flag
FE:         equ   1           ;(bit #1) Rx framing error
PF:         equ   0           ;(bit #0) Rx parity failed

mTDRE:      equ    %10000000  ;(bit #7) Tx data register empty
mTC:        equ    %01000000  ;(bit #6) transmit complete
mRDRF:      equ    %00100000  ;(bit #5) Rx data register full
mIDLE:      equ    %00010000  ;(bit #4) idle line detected
mOR:        equ    %00001000  ;(bit #3) Rx over run
mNF:        equ    %00000100  ;(bit #2) Rx noise flag
mFE:        equ    %00000010  ;(bit #1) Rx framing error
mPF:        equ    %00000001  ;(bit #0) Rx parity failed

  IF RCS_ENA = 1
RCS         EQU     $80   	; READ COMMAND SUPPORTED
  ELSE
RCS         EQU     0     	; READ COMMAND unSUPPORTED
  ENDIF

VER_NUM     EQU     10      ; FC protocol version number

IDENTS      MACRO

			      DC.B	'QE'

          IF SIZE = 64
            DC.B     '64'    ; 64kB string
          ENDIF
          IF SIZE = 96
            DC.B     '96'    ; 96kB string
          ENDIF
          IF SIZE = 128
            DC.B     '128'   ; 128kB string
          ENDIF

          IFDEF IRQOPTION
            DC.B     '-irq'     ; IRQ option used
          ENDIF

            DC.B    0
            ENDM

ERBLK_LEN	EQU		512
WRBLK_LEN	EQU		128      

ADDR24  MACRO
          DC.B  (\1) / $10000
          DC.W  (\1) & $0FFFF
        ENDM

   
REL_VECT	EQU 	$FBA0	; newly relocated int. vectors
INT_VECT	EQU		$FFC0	; start of table of original vectors

    	XDEF	main
    	XDEF	VEC1
    	XDEF	VEC2
    	XDEF	VEC3
    	XDEF	VEC4
    	XDEF	VEC5
    	XDEF	VEC6
    	XDEF	VEC7
    	XDEF	VEC8
    	XDEF	VEC9
    	XDEF	VEC10
    	XDEF	VEC11
    	XDEF	VEC12
    	XDEF	VEC13
    	XDEF	VEC14
    	XDEF	VEC15
    	XDEF	VEC16
    	XDEF	VEC17
    	XDEF	VEC18
    	XDEF	VEC19
    	XDEF	VEC20
    	XDEF	VEC21
    	XDEF	VEC22
    	XDEF	VEC23
    	XDEF	VEC24
    	XDEF	VEC25
    	XDEF	VEC26
    	XDEF	VEC27
    	XDEF	VEC28
    	XDEF	VEC29
    	XDEF	VEC30
    	XDEF	VEC31

			XDEF	main
;*******************************************************************************************
  
WR_DATA		EQU	    'W'
RD_DATA		EQU	    'R'
ENDPRG		EQU	    'Q'
ERASE	  	EQU	    'E'
ACK		    EQU	    $FC
IDENT		  EQU	    'I'

T100MS		EQU	    255

ILOP      MACRO
            STOP      ; illegal as of this config
            ;DC.W    $9E9E   ; this is illegal operation code for CPUV4
          ENDM
;*******************************************************************************************
MY_ZEROPAGE:	SECTION  SHORT

ADRS: 	DS.W	1
ADRR: 	DS.W	1
LEN:  	DS.B	1
STAT: 	DS.B	1
STACK:	DS.W	1

DEFAULT_RAM:    SECTION

DATA:	  DS.B    WRBLK_LEN

;*******************************************************************************************
DEFAULT_ROM:	SECTION
     

ID_STRING:

          IF SIZE = 64
		    DC.B	2				    ; number of Flash blocks
        ADDR24  ROMStart  ; START ADDRESS OF FLASH	
        ADDR24  REL_VECT  ; END ADDRESS OF FLASH																						    
        ADDR24  PPAGE_2Start
        ADDR24  PPAGE_2End+1
          ENDIF

          IF SIZE = 96
		    DC.B	4				    ; number of Flash blocks
        ADDR24  ROMStart  ; START ADDRESS OF FLASH	
        ADDR24  REL_VECT  ; END ADDRESS OF FLASH																						    
        ADDR24  PPAGE_2Start
        ADDR24  PPAGE_2End+1
        ADDR24  PPAGE_4Start
        ADDR24  PPAGE_4End+1 
        ADDR24  PPAGE_5Start
        ADDR24  PPAGE_5End+1 
          ENDIF

          IF SIZE = 128
		    DC.B	6				    ; number of Flash blocks
        ADDR24  ROMStart  ; START ADDRESS OF FLASH	
        ADDR24  REL_VECT  ; END ADDRESS OF FLASH																						    
        ADDR24  PPAGE_2Start
        ADDR24  PPAGE_2End+1
        ADDR24  PPAGE_4Start
        ADDR24  PPAGE_4End+1 
        ADDR24  PPAGE_5Start
        ADDR24  PPAGE_5End+1 
        ADDR24  PPAGE_6Start
        ADDR24  PPAGE_6End+1 
        ADDR24  PPAGE_7Start
        ADDR24  PPAGE_7End+1 
          ENDIF


		    DC.W	REL_VECT		; POINTER TO APPLICATION VECTOR TABLE
        DC.W	INT_VECT		; POINTER TO BEGINING OF FLASH INT. VECTORS
        DC.W	ERBLK_LEN		; ERASE BLCK LENGTH OF FLASH ALG.
        DC.W	WRBLK_LEN		; WRITE BLCK LENGTH OF FLASH ALG.

		IDENTS
ID_STRING_END:

    	XDEF 	MY_NVPROT	
    	XDEF	MY_NVOPT 	

;*******************************************************************************************
APL_VECT_ROM:	SECTION

APL_VECT:
VEC0:   JMP		  main            ; vector 0
VEC1:   JMP     main            ; vector 1
VEC2:   JMP     main            ; vector 2
VEC3:   JMP     main            ; vector 3
VEC4:   JMP     main            ; vector 4
VEC5:   JMP     main            ; vector 5
VEC6:   JMP     main            ; vector 6
VEC7:   JMP     main            ; vector 7
VEC8:   JMP     main            ; vector 8
VEC9:   JMP     main            ; vector 9
VEC10:  JMP     main            ; vector 10
VEC11:  JMP     main            ; vector 11
VEC12:  JMP     main            ; vector 12
VEC13:  JMP     main            ; vector 13
VEC14:  JMP     main            ; vector 14
VEC15:  JMP     main            ; vector 15
VEC16:  JMP     main            ; vector 16
VEC17:  JMP     main            ; vector 17
VEC18:  JMP     main            ; vector 18
VEC19:  JMP     main            ; vector 19
VEC20:  JMP     main            ; vector 20

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