📄 mc9s08qe128.inc
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SCI1C2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF)
SCI1C2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC)
SCI1C2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE)
; bit position masks
mSCI1C2_SBK: equ %00000001
mSCI1C2_RWU: equ %00000010
mSCI1C2_RE: equ %00000100
mSCI1C2_TE: equ %00001000
mSCI1C2_ILIE: equ %00010000
mSCI1C2_RIE: equ %00100000
mSCI1C2_TCIE: equ %01000000
mSCI1C2_TIE: equ %10000000
;*** SCI1S1 - SCI1 Status Register 1; 0x00000024 ***
SCI1S1: equ $00000024 ;*** SCI1S1 - SCI1 Status Register 1; 0x00000024 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1S1_PF: equ 0 ; Parity Error Flag
SCI1S1_FE: equ 1 ; Framing Error Flag
SCI1S1_NF: equ 2 ; Noise Flag
SCI1S1_OR: equ 3 ; Receiver Overrun Flag
SCI1S1_IDLE: equ 4 ; Idle Line Flag
SCI1S1_RDRF: equ 5 ; Receive Data Register Full Flag
SCI1S1_TC: equ 6 ; Transmission Complete Flag
SCI1S1_TDRE: equ 7 ; Transmit Data Register Empty Flag
; bit position masks
mSCI1S1_PF: equ %00000001
mSCI1S1_FE: equ %00000010
mSCI1S1_NF: equ %00000100
mSCI1S1_OR: equ %00001000
mSCI1S1_IDLE: equ %00010000
mSCI1S1_RDRF: equ %00100000
mSCI1S1_TC: equ %01000000
mSCI1S1_TDRE: equ %10000000
;*** SCI1S2 - SCI1 Status Register 2; 0x00000025 ***
SCI1S2: equ $00000025 ;*** SCI1S2 - SCI1 Status Register 2; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1S2_RAF: equ 0 ; Receiver Active Flag
SCI1S2_LBKDE: equ 1 ; LIN Break Detection Enable
SCI1S2_BRK13: equ 2 ; Break Character Generation Length
SCI1S2_RWUID: equ 3 ; Receive Wake Up Idle Detect
SCI1S2_RXINV: equ 4 ; Receive Data Inversion
SCI1S2_RXEDGIF: equ 6 ; RxD Pin Active Edge Interrupt Flag
SCI1S2_LBKDIF: equ 7 ; LIN Break Detect Interrupt Flag
; bit position masks
mSCI1S2_RAF: equ %00000001
mSCI1S2_LBKDE: equ %00000010
mSCI1S2_BRK13: equ %00000100
mSCI1S2_RWUID: equ %00001000
mSCI1S2_RXINV: equ %00010000
mSCI1S2_RXEDGIF: equ %01000000
mSCI1S2_LBKDIF: equ %10000000
;*** SCI1C3 - SCI1 Control Register 3; 0x00000026 ***
SCI1C3: equ $00000026 ;*** SCI1C3 - SCI1 Control Register 3; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1C3_PEIE: equ 0 ; Parity Error Interrupt Enable
SCI1C3_FEIE: equ 1 ; Framing Error Interrupt Enable
SCI1C3_NEIE: equ 2 ; Noise Error Interrupt Enable
SCI1C3_ORIE: equ 3 ; Overrun Interrupt Enable
SCI1C3_TXINV: equ 4 ; Transmit Data Inversion
SCI1C3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode
SCI1C3_T8: equ 6 ; Ninth Data Bit for Transmitter
SCI1C3_R8: equ 7 ; Ninth Data Bit for Receiver
; bit position masks
mSCI1C3_PEIE: equ %00000001
mSCI1C3_FEIE: equ %00000010
mSCI1C3_NEIE: equ %00000100
mSCI1C3_ORIE: equ %00001000
mSCI1C3_TXINV: equ %00010000
mSCI1C3_TXDIR: equ %00100000
mSCI1C3_T8: equ %01000000
mSCI1C3_R8: equ %10000000
;*** SCI1D - SCI1 Data Register; 0x00000027 ***
SCI1D: equ $00000027 ;*** SCI1D - SCI1 Data Register; 0x00000027 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1D_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCI1D_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCI1D_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCI1D_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCI1D_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCI1D_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCI1D_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCI1D_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCI1D_R0_T0: equ %00000001
mSCI1D_R1_T1: equ %00000010
mSCI1D_R2_T2: equ %00000100
mSCI1D_R3_T3: equ %00001000
mSCI1D_R4_T4: equ %00010000
mSCI1D_R5_T5: equ %00100000
mSCI1D_R6_T6: equ %01000000
mSCI1D_R7_T7: equ %10000000
;*** SPI1C1 - SPI1 Control Register 1; 0x00000028 ***
SPI1C1: equ $00000028 ;*** SPI1C1 - SPI1 Control Register 1; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1C1_LSBFE: equ 0 ; LSB First (Shifter Direction)
SPI1C1_SSOE: equ 1 ; Slave Select Output Enable
SPI1C1_CPHA: equ 2 ; Clock Phase
SPI1C1_CPOL: equ 3 ; Clock Polarity
SPI1C1_MSTR: equ 4 ; Master/Slave Mode Select
SPI1C1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable
SPI1C1_SPE: equ 6 ; SPI System Enable
SPI1C1_SPIE: equ 7 ; SPI Interrupt Enable (for SPRF and MODF)
; bit position masks
mSPI1C1_LSBFE: equ %00000001
mSPI1C1_SSOE: equ %00000010
mSPI1C1_CPHA: equ %00000100
mSPI1C1_CPOL: equ %00001000
mSPI1C1_MSTR: equ %00010000
mSPI1C1_SPTIE: equ %00100000
mSPI1C1_SPE: equ %01000000
mSPI1C1_SPIE: equ %10000000
;*** SPI1C2 - SPI1 Control Register 2; 0x00000029 ***
SPI1C2: equ $00000029 ;*** SPI1C2 - SPI1 Control Register 2; 0x00000029 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1C2_SPC0: equ 0 ; SPI Pin Control 0
SPI1C2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPI1C2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPI1C2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
mSPI1C2_SPC0: equ %00000001
mSPI1C2_SPISWAI: equ %00000010
mSPI1C2_BIDIROE: equ %00001000
mSPI1C2_MODFEN: equ %00010000
;*** SPI1BR - SPI1 Baud Rate Register; 0x0000002A ***
SPI1BR: equ $0000002A ;*** SPI1BR - SPI1 Baud Rate Register; 0x0000002A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1BR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPI1BR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPI1BR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPI1BR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPI1BR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPI1BR_SPPR2: equ 6 ; SPI Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPI1BR_SPR0: equ %00000001
mSPI1BR_SPR1: equ %00000010
mSPI1BR_SPR2: equ %00000100
mSPI1BR_SPPR0: equ %00010000
mSPI1BR_SPPR1: equ %00100000
mSPI1BR_SPPR2: equ %01000000
;*** SPI1S - SPI1 Status Register; 0x0000002B ***
SPI1S: equ $0000002B ;*** SPI1S - SPI1 Status Register; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1S_MODF: equ 4 ; Master Mode Fault Flag
SPI1S_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPI1S_SPRF: equ 7 ; SPI Read Buffer Full Flag
; bit position masks
mSPI1S_MODF: equ %00010000
mSPI1S_SPTEF: equ %00100000
mSPI1S_SPRF: equ %10000000
;*** SPI1D - SPI1 Data Register; 0x0000002D ***
SPI1D: equ $0000002D ;*** SPI1D - SPI1 Data Register; 0x0000002D ***
;*** PTJD - Port J Data Register; 0x0000002E ***
PTJD: equ $0000002E ;*** PTJD - Port J Data Register; 0x0000002E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTJD_PTJD0: equ 0 ; Port J Data Register Bit 0
PTJD_PTJD1: equ 1 ; Port J Data Register Bit 1
PTJD_PTJD2: equ 2 ; Port J Data Register Bit 2
PTJD_PTJD3: equ 3 ; Port J Data Register Bit 3
PTJD_PTJD4: equ 4 ; Port J Data Register Bit 4
PTJD_PTJD5: equ 5 ; Port J Data Register Bit 5
PTJD_PTJD6: equ 6 ; Port J Data Register Bit 6
PTJD_PTJD7: equ 7 ; Port J Data Register Bit 7
; bit position masks
mPTJD_PTJD0: equ %00000001
mPTJD_PTJD1: equ %00000010
mPTJD_PTJD2: equ %00000100
mPTJD_PTJD3: equ %00001000
mPTJD_PTJD4: equ %00010000
mPTJD_PTJD5: equ %00100000
mPTJD_PTJD6: equ %01000000
mPTJD_PTJD7: equ %10000000
;*** PTJDD - Port J Data Direction Register; 0x0000002F ***
PTJDD: equ $0000002F ;*** PTJDD - Port J Data Direction Register; 0x0000002F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTJDD_PTJDD0: equ 0 ; Data Direction for Port J Bit 0
PTJDD_PTJDD1: equ 1 ; Data Direction for Port J Bit 1
PTJDD_PTJDD2: equ 2 ; Data Direction for Port J Bit 2
PTJDD_PTJDD3: equ 3 ; Data Direction for Port J Bit 3
PTJDD_PTJDD4: equ 4 ; Data Direction for Port J Bit 4
PTJDD_PTJDD5: equ 5 ; Data Direction for Port J Bit 5
PTJDD_PTJDD6: equ 6 ; Data Direction for Port J Bit 6
PTJDD_PTJDD7: equ 7 ; Data Direction for Port J Bit 7
; bit position masks
mPTJDD_PTJDD0: equ %00000001
mPTJDD_PTJDD1: equ %00000010
mPTJDD_PTJDD2: equ %00000100
mPTJDD_PTJDD3: equ %00001000
mPTJDD_PTJDD4: equ %00010000
mPTJDD_PTJDD5: equ %00100000
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