⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 mc9s08qe128.inc

📁 M68HC08及HCS08系列单片机bootloader引导程序源码/示例
💻 INC
📖 第 1 页 / 共 5 页
字号:
mAPCTL3_ADPC22:     equ    %01000000
mAPCTL3_ADPC23:     equ    %10000000


;*** ACMP1SC - ACMP1 Status and Control Register; 0x0000001A ***
ACMP1SC:            equ    $0000001A                                ;*** ACMP1SC - ACMP1 Status and Control Register; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP1SC_ACMOD0:     equ    0                                         ; Analog Comparator Mode Bit 0
ACMP1SC_ACMOD1:     equ    1                                         ; Analog Comparator Mode Bit 1
ACMP1SC_ACOPE:      equ    2                                         ; Analog Comparator Output Pin Enable
ACMP1SC_ACO:        equ    3                                         ; Analog Comparator Output
ACMP1SC_ACIE:       equ    4                                         ; Analog Comparator Interrupt Enable
ACMP1SC_ACF:        equ    5                                         ; Analog Comparator Flag
ACMP1SC_ACBGS:      equ    6                                         ; Analog Comparator Bandgap Select
ACMP1SC_ACME:       equ    7                                         ; Analog Comparator Module Enable
; bit position masks
mACMP1SC_ACMOD0:    equ    %00000001
mACMP1SC_ACMOD1:    equ    %00000010
mACMP1SC_ACOPE:     equ    %00000100
mACMP1SC_ACO:       equ    %00001000
mACMP1SC_ACIE:      equ    %00010000
mACMP1SC_ACF:       equ    %00100000
mACMP1SC_ACBGS:     equ    %01000000
mACMP1SC_ACME:      equ    %10000000


;*** ACMP2SC - ACMP2 Status and Control Register; 0x0000001B ***
ACMP2SC:            equ    $0000001B                                ;*** ACMP2SC - ACMP2 Status and Control Register; 0x0000001B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP2SC_ACMOD0:     equ    0                                         ; Analog Comparator Mode Bit 0
ACMP2SC_ACMOD1:     equ    1                                         ; Analog Comparator Mode Bit 1
ACMP2SC_ACOPE:      equ    2                                         ; Analog Comparator Output Pin Enable
ACMP2SC_ACO:        equ    3                                         ; Analog Comparator Output
ACMP2SC_ACIE:       equ    4                                         ; Analog Comparator Interrupt Enable
ACMP2SC_ACF:        equ    5                                         ; Analog Comparator Flag
ACMP2SC_ACBGS:      equ    6                                         ; Analog Comparator Bandgap Select
ACMP2SC_ACME:       equ    7                                         ; Analog Comparator Module Enable
; bit position masks
mACMP2SC_ACMOD0:    equ    %00000001
mACMP2SC_ACMOD1:    equ    %00000010
mACMP2SC_ACOPE:     equ    %00000100
mACMP2SC_ACO:       equ    %00001000
mACMP2SC_ACIE:      equ    %00010000
mACMP2SC_ACF:       equ    %00100000
mACMP2SC_ACBGS:     equ    %01000000
mACMP2SC_ACME:      equ    %10000000


;*** PTGD - Port G Data Register; 0x0000001C ***
PTGD:               equ    $0000001C                                ;*** PTGD - Port G Data Register; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTGD_PTGD0:         equ    0                                         ; Port G Data Register Bit 0
PTGD_PTGD1:         equ    1                                         ; Port G Data Register Bit 1
PTGD_PTGD2:         equ    2                                         ; Port G Data Register Bit 2
PTGD_PTGD3:         equ    3                                         ; Port G Data Register Bit 3
PTGD_PTGD4:         equ    4                                         ; Port G Data Register Bit 4
PTGD_PTGD5:         equ    5                                         ; Port G Data Register Bit 5
PTGD_PTGD6:         equ    6                                         ; Port G Data Register Bit 6
PTGD_PTGD7:         equ    7                                         ; Port G Data Register Bit 7
; bit position masks
mPTGD_PTGD0:        equ    %00000001
mPTGD_PTGD1:        equ    %00000010
mPTGD_PTGD2:        equ    %00000100
mPTGD_PTGD3:        equ    %00001000
mPTGD_PTGD4:        equ    %00010000
mPTGD_PTGD5:        equ    %00100000
mPTGD_PTGD6:        equ    %01000000
mPTGD_PTGD7:        equ    %10000000


;*** PTGDD - Port G Data Direction Register; 0x0000001D ***
PTGDD:              equ    $0000001D                                ;*** PTGDD - Port G Data Direction Register; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTGDD_PTGDD0:       equ    0                                         ; Data Direction for Port G Bit 0
PTGDD_PTGDD1:       equ    1                                         ; Data Direction for Port G Bit 1
PTGDD_PTGDD2:       equ    2                                         ; Data Direction for Port G Bit 2
PTGDD_PTGDD3:       equ    3                                         ; Data Direction for Port G Bit 3
PTGDD_PTGDD4:       equ    4                                         ; Data Direction for Port G Bit 4
PTGDD_PTGDD5:       equ    5                                         ; Data Direction for Port G Bit 5
PTGDD_PTGDD6:       equ    6                                         ; Data Direction for Port G Bit 6
PTGDD_PTGDD7:       equ    7                                         ; Data Direction for Port G Bit 7
; bit position masks
mPTGDD_PTGDD0:      equ    %00000001
mPTGDD_PTGDD1:      equ    %00000010
mPTGDD_PTGDD2:      equ    %00000100
mPTGDD_PTGDD3:      equ    %00001000
mPTGDD_PTGDD4:      equ    %00010000
mPTGDD_PTGDD5:      equ    %00100000
mPTGDD_PTGDD6:      equ    %01000000
mPTGDD_PTGDD7:      equ    %10000000


;*** PTHD - Port H Data Register; 0x0000001E ***
PTHD:               equ    $0000001E                                ;*** PTHD - Port H Data Register; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTHD_PTHD0:         equ    0                                         ; Port H Data Register Bit 0
PTHD_PTHD1:         equ    1                                         ; Port H Data Register Bit 1
PTHD_PTHD2:         equ    2                                         ; Port H Data Register Bit 2
PTHD_PTHD3:         equ    3                                         ; Port H Data Register Bit 3
PTHD_PTHD4:         equ    4                                         ; Port H Data Register Bit 4
PTHD_PTHD5:         equ    5                                         ; Port H Data Register Bit 5
PTHD_PTHD6:         equ    6                                         ; Port H Data Register Bit 6
PTHD_PTHD7:         equ    7                                         ; Port H Data Register Bit 7
; bit position masks
mPTHD_PTHD0:        equ    %00000001
mPTHD_PTHD1:        equ    %00000010
mPTHD_PTHD2:        equ    %00000100
mPTHD_PTHD3:        equ    %00001000
mPTHD_PTHD4:        equ    %00010000
mPTHD_PTHD5:        equ    %00100000
mPTHD_PTHD6:        equ    %01000000
mPTHD_PTHD7:        equ    %10000000


;*** PTHDD - Port H Data Direction Register; 0x0000001F ***
PTHDD:              equ    $0000001F                                ;*** PTHDD - Port H Data Direction Register; 0x0000001F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTHDD_PTHDD0:       equ    0                                         ; Data Direction for Port H Bit 0
PTHDD_PTHDD1:       equ    1                                         ; Data Direction for Port H Bit 1
PTHDD_PTHDD2:       equ    2                                         ; Data Direction for Port H Bit 2
PTHDD_PTHDD3:       equ    3                                         ; Data Direction for Port H Bit 3
PTHDD_PTHDD4:       equ    4                                         ; Data Direction for Port H Bit 4
PTHDD_PTHDD5:       equ    5                                         ; Data Direction for Port H Bit 5
PTHDD_PTHDD6:       equ    6                                         ; Data Direction for Port H Bit 6
PTHDD_PTHDD7:       equ    7                                         ; Data Direction for Port H Bit 7
; bit position masks
mPTHDD_PTHDD0:      equ    %00000001
mPTHDD_PTHDD1:      equ    %00000010
mPTHDD_PTHDD2:      equ    %00000100
mPTHDD_PTHDD3:      equ    %00001000
mPTHDD_PTHDD4:      equ    %00010000
mPTHDD_PTHDD5:      equ    %00100000
mPTHDD_PTHDD6:      equ    %01000000
mPTHDD_PTHDD7:      equ    %10000000


;*** SCI1BD - SCI1 Baud Rate Register; 0x00000020 ***
SCI1BD:             equ    $00000020                                ;*** SCI1BD - SCI1 Baud Rate Register; 0x00000020 ***


;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000020 ***
SCI1BDH:            equ    $00000020                                ;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1BDH_SBR8:       equ    0                                         ; Baud Rate Modulo Divisor Bit 8
SCI1BDH_SBR9:       equ    1                                         ; Baud Rate Modulo Divisor Bit 9
SCI1BDH_SBR10:      equ    2                                         ; Baud Rate Modulo Divisor Bit 10
SCI1BDH_SBR11:      equ    3                                         ; Baud Rate Modulo Divisor Bit 11
SCI1BDH_SBR12:      equ    4                                         ; Baud Rate Modulo Divisor Bit 12
SCI1BDH_RXEDGIE:    equ    6                                         ; RxD Input Active Edge Interrupt Enable (for RXEDGIF)
SCI1BDH_LBKDIE:     equ    7                                         ; LIN Break Detect Interrupt Enable (for LBKDIF)
; bit position masks
mSCI1BDH_SBR8:      equ    %00000001
mSCI1BDH_SBR9:      equ    %00000010
mSCI1BDH_SBR10:     equ    %00000100
mSCI1BDH_SBR11:     equ    %00001000
mSCI1BDH_SBR12:     equ    %00010000
mSCI1BDH_RXEDGIE:   equ    %01000000
mSCI1BDH_LBKDIE:    equ    %10000000


;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000021 ***
SCI1BDL:            equ    $00000021                                ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000021 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1BDL_SBR0:       equ    0                                         ; Baud Rate Modulo Divisor Bit 0
SCI1BDL_SBR1:       equ    1                                         ; Baud Rate Modulo Divisor Bit 1
SCI1BDL_SBR2:       equ    2                                         ; Baud Rate Modulo Divisor Bit 2
SCI1BDL_SBR3:       equ    3                                         ; Baud Rate Modulo Divisor Bit 3
SCI1BDL_SBR4:       equ    4                                         ; Baud Rate Modulo Divisor Bit 4
SCI1BDL_SBR5:       equ    5                                         ; Baud Rate Modulo Divisor Bit 5
SCI1BDL_SBR6:       equ    6                                         ; Baud Rate Modulo Divisor Bit 6
SCI1BDL_SBR7:       equ    7                                         ; Baud Rate Modulo Divisor Bit 7
; bit position masks
mSCI1BDL_SBR0:      equ    %00000001
mSCI1BDL_SBR1:      equ    %00000010
mSCI1BDL_SBR2:      equ    %00000100
mSCI1BDL_SBR3:      equ    %00001000
mSCI1BDL_SBR4:      equ    %00010000
mSCI1BDL_SBR5:      equ    %00100000
mSCI1BDL_SBR6:      equ    %01000000
mSCI1BDL_SBR7:      equ    %10000000


;*** SCI1C1 - SCI1 Control Register 1; 0x00000022 ***
SCI1C1:             equ    $00000022                                ;*** SCI1C1 - SCI1 Control Register 1; 0x00000022 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1C1_PT:          equ    0                                         ; Parity Type
SCI1C1_PE:          equ    1                                         ; Parity Enable
SCI1C1_ILT:         equ    2                                         ; Idle Line Type Select
SCI1C1_WAKE:        equ    3                                         ; Receiver Wakeup Method Select
SCI1C1_M:           equ    4                                         ; 9-Bit or 8-Bit Mode Select
SCI1C1_RSRC:        equ    5                                         ; Receiver Source Select
SCI1C1_SCISWAI:     equ    6                                         ; SCI Stops in Wait Mode
SCI1C1_LOOPS:       equ    7                                         ; Loop Mode Select
; bit position masks
mSCI1C1_PT:         equ    %00000001
mSCI1C1_PE:         equ    %00000010
mSCI1C1_ILT:        equ    %00000100
mSCI1C1_WAKE:       equ    %00001000
mSCI1C1_M:          equ    %00010000
mSCI1C1_RSRC:       equ    %00100000
mSCI1C1_SCISWAI:    equ    %01000000
mSCI1C1_LOOPS:      equ    %10000000


;*** SCI1C2 - SCI1 Control Register 2; 0x00000023 ***
SCI1C2:             equ    $00000023                                ;*** SCI1C2 - SCI1 Control Register 2; 0x00000023 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1C2_SBK:         equ    0                                         ; Send Break
SCI1C2_RWU:         equ    1                                         ; Receiver Wakeup Control
SCI1C2_RE:          equ    2                                         ; Receiver Enable
SCI1C2_TE:          equ    3                                         ; Transmitter Enable
SCI1C2_ILIE:        equ    4                                         ; Idle Line Interrupt Enable (for IDLE)

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -