mc9s08dz60.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

mTPM1C4VH_BIT9:     equ    %00000010
mTPM1C4VH_BIT10:    equ    %00000100
mTPM1C4VH_BIT11:    equ    %00001000
mTPM1C4VH_BIT12:    equ    %00010000
mTPM1C4VH_BIT13:    equ    %00100000
mTPM1C4VH_BIT14:    equ    %01000000
mTPM1C4VH_BIT15:    equ    %10000000


;*** TPM1C4VL - TPM 1 Timer Channel 4 Value Register Low; 0x00000033 ***
TPM1C4VL:           equ    $00000033                                ;*** TPM1C4VL - TPM 1 Timer Channel 4 Value Register Low; 0x00000033 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C4VL_BIT0:      equ    0                                         ; Timer Channel 4 Value Bit 0
TPM1C4VL_BIT1:      equ    1                                         ; Timer Channel 4 Value Bit 1
TPM1C4VL_BIT2:      equ    2                                         ; Timer Channel 4 Value Bit 2
TPM1C4VL_BIT3:      equ    3                                         ; Timer Channel 4 Value Bit 3
TPM1C4VL_BIT4:      equ    4                                         ; Timer Channel 4 Value Bit 4
TPM1C4VL_BIT5:      equ    5                                         ; Timer Channel 4 Value Bit 5
TPM1C4VL_BIT6:      equ    6                                         ; Timer Channel 4 Value Bit 6
TPM1C4VL_BIT7:      equ    7                                         ; Timer Channel 4 Value Bit 7
; bit position masks
mTPM1C4VL_BIT0:     equ    %00000001
mTPM1C4VL_BIT1:     equ    %00000010
mTPM1C4VL_BIT2:     equ    %00000100
mTPM1C4VL_BIT3:     equ    %00001000
mTPM1C4VL_BIT4:     equ    %00010000
mTPM1C4VL_BIT5:     equ    %00100000
mTPM1C4VL_BIT6:     equ    %01000000
mTPM1C4VL_BIT7:     equ    %10000000


;*** TPM1C5SC - TPM 1 Timer Channel 5 Status and Control Register; 0x00000034 ***
TPM1C5SC:           equ    $00000034                                ;*** TPM1C5SC - TPM 1 Timer Channel 5 Status and Control Register; 0x00000034 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C5SC_ELS5A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C5SC_ELS5B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C5SC_MS5A:      equ    4                                         ; Mode Select A for TPM Channel 5
TPM1C5SC_MS5B:      equ    5                                         ; Mode Select B for TPM Channel 5
TPM1C5SC_CH5IE:     equ    6                                         ; Channel 5 Interrupt Enable
TPM1C5SC_CH5F:      equ    7                                         ; Channel 5 Flag
; bit position masks
mTPM1C5SC_ELS5A:    equ    %00000100
mTPM1C5SC_ELS5B:    equ    %00001000
mTPM1C5SC_MS5A:     equ    %00010000
mTPM1C5SC_MS5B:     equ    %00100000
mTPM1C5SC_CH5IE:    equ    %01000000
mTPM1C5SC_CH5F:     equ    %10000000


;*** TPM1C5V - TPM 1 Timer Channel 5 Value Register; 0x00000035 ***
TPM1C5V:            equ    $00000035                                ;*** TPM1C5V - TPM 1 Timer Channel 5 Value Register; 0x00000035 ***


;*** TPM1C5VH - TPM 1 Timer Channel 5 Value Register High; 0x00000035 ***
TPM1C5VH:           equ    $00000035                                ;*** TPM1C5VH - TPM 1 Timer Channel 5 Value Register High; 0x00000035 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C5VH_BIT8:      equ    0                                         ; Timer Channel 5 Value Bit 8
TPM1C5VH_BIT9:      equ    1                                         ; Timer Channel 5 Value Bit 9
TPM1C5VH_BIT10:     equ    2                                         ; Timer Channel 5 Value Bit 10
TPM1C5VH_BIT11:     equ    3                                         ; Timer Channel 5 Value Bit 11
TPM1C5VH_BIT12:     equ    4                                         ; Timer Channel 5 Value Bit 12
TPM1C5VH_BIT13:     equ    5                                         ; Timer Channel 5 Value Bit 13
TPM1C5VH_BIT14:     equ    6                                         ; Timer Channel 5 Value Bit 14
TPM1C5VH_BIT15:     equ    7                                         ; Timer Channel 5 Value Bit 15
; bit position masks
mTPM1C5VH_BIT8:     equ    %00000001
mTPM1C5VH_BIT9:     equ    %00000010
mTPM1C5VH_BIT10:    equ    %00000100
mTPM1C5VH_BIT11:    equ    %00001000
mTPM1C5VH_BIT12:    equ    %00010000
mTPM1C5VH_BIT13:    equ    %00100000
mTPM1C5VH_BIT14:    equ    %01000000
mTPM1C5VH_BIT15:    equ    %10000000


;*** TPM1C5VL - TPM 1 Timer Channel 5 Value Register Low; 0x00000036 ***
TPM1C5VL:           equ    $00000036                                ;*** TPM1C5VL - TPM 1 Timer Channel 5 Value Register Low; 0x00000036 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C5VL_BIT0:      equ    0                                         ; Timer Channel 5 Value Bit 0
TPM1C5VL_BIT1:      equ    1                                         ; Timer Channel 5 Value Bit 1
TPM1C5VL_BIT2:      equ    2                                         ; Timer Channel 5 Value Bit 2
TPM1C5VL_BIT3:      equ    3                                         ; Timer Channel 5 Value Bit 3
TPM1C5VL_BIT4:      equ    4                                         ; Timer Channel 5 Value Bit 4
TPM1C5VL_BIT5:      equ    5                                         ; Timer Channel 5 Value Bit 5
TPM1C5VL_BIT6:      equ    6                                         ; Timer Channel 5 Value Bit 6
TPM1C5VL_BIT7:      equ    7                                         ; Timer Channel 5 Value Bit 7
; bit position masks
mTPM1C5VL_BIT0:     equ    %00000001
mTPM1C5VL_BIT1:     equ    %00000010
mTPM1C5VL_BIT2:     equ    %00000100
mTPM1C5VL_BIT3:     equ    %00001000
mTPM1C5VL_BIT4:     equ    %00010000
mTPM1C5VL_BIT5:     equ    %00100000
mTPM1C5VL_BIT6:     equ    %01000000
mTPM1C5VL_BIT7:     equ    %10000000


;*** SCI1BD - SCI1 Baud Rate Register; 0x00000038 ***
SCI1BD:             equ    $00000038                                ;*** SCI1BD - SCI1 Baud Rate Register; 0x00000038 ***


;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000038 ***
SCI1BDH:            equ    $00000038                                ;*** SCI1BDH - SCI1 Baud Rate Register High; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1BDH_SBR8:       equ    0                                         ; Baud Rate Modulo Divisor Bit 8
SCI1BDH_SBR9:       equ    1                                         ; Baud Rate Modulo Divisor Bit 9
SCI1BDH_SBR10:      equ    2                                         ; Baud Rate Modulo Divisor Bit 10
SCI1BDH_SBR11:      equ    3                                         ; Baud Rate Modulo Divisor Bit 11
SCI1BDH_SBR12:      equ    4                                         ; Baud Rate Modulo Divisor Bit 12
SCI1BDH_RXEDGIE:    equ    6                                         ; RxD Input Active Edge Interrupt Enable (for RXEDGIF)
SCI1BDH_LBKDIE:     equ    7                                         ; LIN Break Detect Interrupt Enable (for LBKDIF)
; bit position masks
mSCI1BDH_SBR8:      equ    %00000001
mSCI1BDH_SBR9:      equ    %00000010
mSCI1BDH_SBR10:     equ    %00000100
mSCI1BDH_SBR11:     equ    %00001000
mSCI1BDH_SBR12:     equ    %00010000
mSCI1BDH_RXEDGIE:   equ    %01000000
mSCI1BDH_LBKDIE:    equ    %10000000


;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000039 ***
SCI1BDL:            equ    $00000039                                ;*** SCI1BDL - SCI1 Baud Rate Register Low; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1BDL_SBR0:       equ    0                                         ; Baud Rate Modulo Divisor Bit 0
SCI1BDL_SBR1:       equ    1                                         ; Baud Rate Modulo Divisor Bit 1
SCI1BDL_SBR2:       equ    2                                         ; Baud Rate Modulo Divisor Bit 2
SCI1BDL_SBR3:       equ    3                                         ; Baud Rate Modulo Divisor Bit 3
SCI1BDL_SBR4:       equ    4                                         ; Baud Rate Modulo Divisor Bit 4
SCI1BDL_SBR5:       equ    5                                         ; Baud Rate Modulo Divisor Bit 5
SCI1BDL_SBR6:       equ    6                                         ; Baud Rate Modulo Divisor Bit 6
SCI1BDL_SBR7:       equ    7                                         ; Baud Rate Modulo Divisor Bit 7
; bit position masks
mSCI1BDL_SBR0:      equ    %00000001
mSCI1BDL_SBR1:      equ    %00000010
mSCI1BDL_SBR2:      equ    %00000100
mSCI1BDL_SBR3:      equ    %00001000
mSCI1BDL_SBR4:      equ    %00010000
mSCI1BDL_SBR5:      equ    %00100000
mSCI1BDL_SBR6:      equ    %01000000
mSCI1BDL_SBR7:      equ    %10000000


;*** SCI1C1 - SCI1 Control Register 1; 0x0000003A ***
SCI1C1:             equ    $0000003A                                ;*** SCI1C1 - SCI1 Control Register 1; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1C1_PT:          equ    0                                         ; Parity Type
SCI1C1_PE:          equ    1                                         ; Parity Enable
SCI1C1_ILT:         equ    2                                         ; Idle Line Type Select
SCI1C1_WAKE:        equ    3                                         ; Receiver Wakeup Method Select
SCI1C1_M:           equ    4                                         ; 9-Bit or 8-Bit Mode Select
SCI1C1_RSRC:        equ    5                                         ; Receiver Source Select
SCI1C1_SCISWAI:     equ    6                                         ; SCI Stops in Wait Mode
SCI1C1_LOOPS:       equ    7                                         ; Loop Mode Select
; bit position masks
mSCI1C1_PT:         equ    %00000001
mSCI1C1_PE:         equ    %00000010
mSCI1C1_ILT:        equ    %00000100
mSCI1C1_WAKE:       equ    %00001000
mSCI1C1_M:          equ    %00010000
mSCI1C1_RSRC:       equ    %00100000
mSCI1C1_SCISWAI:    equ    %01000000
mSCI1C1_LOOPS:      equ    %10000000


;*** SCI1C2 - SCI1 Control Register 2; 0x0000003B ***
SCI1C2:             equ    $0000003B                                ;*** SCI1C2 - SCI1 Control Register 2; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1C2_SBK:         equ    0                                         ; Send Break
SCI1C2_RWU:         equ    1                                         ; Receiver Wakeup Control
SCI1C2_RE:          equ    2                                         ; Receiver Enable
SCI1C2_TE:          equ    3                                         ; Transmitter Enable
SCI1C2_ILIE:        equ    4                                         ; Idle Line Interrupt Enable (for IDLE)
SCI1C2_RIE:         equ    5                                         ; Receiver Interrupt Enable (for RDRF)
SCI1C2_TCIE:        equ    6                                         ; Transmission Complete Interrupt Enable (for TC)
SCI1C2_TIE:         equ    7                                         ; Transmit Interrupt Enable (for TDRE)
; bit position masks
mSCI1C2_SBK:        equ    %00000001
mSCI1C2_RWU:        equ    %00000010
mSCI1C2_RE:         equ    %00000100
mSCI1C2_TE:         equ    %00001000
mSCI1C2_ILIE:       equ    %00010000
mSCI1C2_RIE:        equ    %00100000
mSCI1C2_TCIE:       equ    %01000000
mSCI1C2_TIE:        equ    %10000000


;*** SCI1S1 - SCI1 Status Register 1; 0x0000003C ***
SCI1S1:             equ    $0000003C                                ;*** SCI1S1 - SCI1 Status Register 1; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1S1_PF:          equ    0                                         ; Parity Error Flag
SCI1S1_FE:          equ    1                                         ; Framing Error Flag
SCI1S1_NF:          equ    2                                         ; Noise Flag
SCI1S1_OR:          equ    3                                         ; Receiver Overrun Flag
SCI1S1_IDLE:        equ    4                                         ; Idle Line Flag
SCI1S1_RDRF:        equ    5                                         ; Receive Data Register Full Flag
SCI1S1_TC:          equ    6                                         ; Transmission Complete Flag
SCI1S1_TDRE:        equ    7                                         ; Transmit Data Register Empty Flag
; bit position masks
mSCI1S1_PF:         equ    %00000001
mSCI1S1_FE:         equ    %00000010
mSCI1S1_NF:         equ    %00000100
mSCI1S1_OR:         equ    %00001000
mSCI1S1_IDLE:       equ    %00010000
mSCI1S1_RDRF:       equ    %00100000
mSCI1S1_TC:         equ    %01000000
mSCI1S1_TDRE:       equ    %10000000


;*** SCI1S2 - SCI1 Status Register 2; 0x0000003D ***
SCI1S2:             equ    $0000003D                                ;*** SCI1S2 - SCI1 Status Register 2; 0x0000003D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCI1S2_RAF:         equ    0                                         ; Receiver Active Flag
SCI1S2_LBKDE:       equ    1                                         ; LIN Break Detection Enable
SCI1S2_BRK13:       equ    2                                         ; Break Character Generation Length
SCI1S2_RWUID:       equ    3                                         ; ReceiveWake Up Idle Detect
SCI1S2_RXINV:       equ    4                                         ; Receive Data Inversion
SCI1S2_RXEDGIF:     equ    6                                         ; RxD Pin Active Edge Interrupt Flag
SCI1S2_LBKD