📄 mc9s08dz60.inc
字号:
mADSC1_ADCH1: equ %00000010
mADSC1_ADCH2: equ %00000100
mADSC1_ADCH3: equ %00001000
mADSC1_ADCH4: equ %00010000
mADSC1_ADCO: equ %00100000
mADSC1_AIEN: equ %01000000
mADSC1_COCO: equ %10000000
;*** ADSC2 - Status and Control Register 2; 0x00000011 ***
ADSC2: equ $00000011 ;*** ADSC2 - Status and Control Register 2; 0x00000011 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADSC2_ACFGT: equ 4 ; Compare Function Greater Than Enable
ADSC2_ACFE: equ 5 ; Compare Function Enable
ADSC2_ADTRG: equ 6 ; Conversion Trigger Select
ADSC2_ADACT: equ 7 ; Conversion Active
; bit position masks
mADSC2_ACFGT: equ %00010000
mADSC2_ACFE: equ %00100000
mADSC2_ADTRG: equ %01000000
mADSC2_ADACT: equ %10000000
;*** ADR - ADC Result Data Right Justified; 0x00000012 ***
ADR: equ $00000012 ;*** ADR - ADC Result Data Right Justified; 0x00000012 ***
;*** ADRH - ADC Result Data Right Justified High; 0x00000012 ***
ADRH: equ $00000012 ;*** ADRH - ADC Result Data Right Justified High; 0x00000012 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADRH_ADR8: equ 0 ; ADC Result Data Bit 8
ADRH_ADR9: equ 1 ; ADC Result Data Bit 9
; bit position masks
mADRH_ADR8: equ %00000001
mADRH_ADR9: equ %00000010
;*** ADRL - ADC Result Data Right Justified Low; 0x00000013 ***
ADRL: equ $00000013 ;*** ADRL - ADC Result Data Right Justified Low; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADRL_ADR0: equ 0 ; ADC Result Data Bit 0
ADRL_ADR1: equ 1 ; ADC Result Data Bit 1
ADRL_ADR2: equ 2 ; ADC Result Data Bit 2
ADRL_ADR3: equ 3 ; ADC Result Data Bit 3
ADRL_ADR4: equ 4 ; ADC Result Data Bit 4
ADRL_ADR5: equ 5 ; ADC Result Data Bit 5
ADRL_ADR6: equ 6 ; ADC Result Data Bit 6
ADRL_ADR7: equ 7 ; ADC Result Data Bit 7
; bit position masks
mADRL_ADR0: equ %00000001
mADRL_ADR1: equ %00000010
mADRL_ADR2: equ %00000100
mADRL_ADR3: equ %00001000
mADRL_ADR4: equ %00010000
mADRL_ADR5: equ %00100000
mADRL_ADR6: equ %01000000
mADRL_ADR7: equ %10000000
;*** ADCV - Compare Value Register; 0x00000014 ***
ADCV: equ $00000014 ;*** ADCV - Compare Value Register; 0x00000014 ***
;*** ADCVH - Compare Value Register High; 0x00000014 ***
ADCVH: equ $00000014 ;*** ADCVH - Compare Value Register High; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCVH_ADCV8: equ 0 ; Compare Function Value 8
ADCVH_ADCV9: equ 1 ; Compare Function Value 9
; bit position masks
mADCVH_ADCV8: equ %00000001
mADCVH_ADCV9: equ %00000010
;*** ADCVL - Compare Value Register Low; 0x00000015 ***
ADCVL: equ $00000015 ;*** ADCVL - Compare Value Register Low; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCVL_ADCV0: equ 0 ; Compare Function Value 0
ADCVL_ADCV1: equ 1 ; Compare Function Value 1
ADCVL_ADCV2: equ 2 ; Compare Function Value 2
ADCVL_ADCV3: equ 3 ; Compare Function Value 3
ADCVL_ADCV4: equ 4 ; Compare Function Value 4
ADCVL_ADCV5: equ 5 ; Compare Function Value 5
ADCVL_ADCV6: equ 6 ; Compare Function Value 6
ADCVL_ADCV7: equ 7 ; Compare Function Value 7
; bit position masks
mADCVL_ADCV0: equ %00000001
mADCVL_ADCV1: equ %00000010
mADCVL_ADCV2: equ %00000100
mADCVL_ADCV3: equ %00001000
mADCVL_ADCV4: equ %00010000
mADCVL_ADCV5: equ %00100000
mADCVL_ADCV6: equ %01000000
mADCVL_ADCV7: equ %10000000
;*** ADCFG - Configuration Register; 0x00000016 ***
ADCFG: equ $00000016 ;*** ADCFG - Configuration Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCFG_ADICLK0: equ 0 ; Input Clock Select Bit 0
ADCFG_ADICLK1: equ 1 ; Input Clock Select Bit 1
ADCFG_MODE0: equ 2 ; Conversion Mode Selection Bit 0
ADCFG_MODE1: equ 3 ; Conversion Mode Selection Bit 1
ADCFG_ADLSMP: equ 4 ; Long Sample Time Configuration
ADCFG_ADIV0: equ 5 ; Clock Divide Select Bit 0
ADCFG_ADIV1: equ 6 ; Clock Divide Select Bit 1
ADCFG_ADLPC: equ 7 ; Low Power Configuration
; bit position masks
mADCFG_ADICLK0: equ %00000001
mADCFG_ADICLK1: equ %00000010
mADCFG_MODE0: equ %00000100
mADCFG_MODE1: equ %00001000
mADCFG_ADLSMP: equ %00010000
mADCFG_ADIV0: equ %00100000
mADCFG_ADIV1: equ %01000000
mADCFG_ADLPC: equ %10000000
;*** APCTL1 - ADC Pin Control 1 Register; 0x00000017 ***
APCTL1: equ $00000017 ;*** APCTL1 - ADC Pin Control 1 Register; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL1_ADPC0: equ 0 ; ADC Pin Control 0
APCTL1_ADPC1: equ 1 ; ADC Pin Control 1
APCTL1_ADPC2: equ 2 ; ADC Pin Control 2
APCTL1_ADPC3: equ 3 ; ADC Pin Control 3
APCTL1_ADPC4: equ 4 ; ADC Pin Control 4
APCTL1_ADPC5: equ 5 ; ADC Pin Control 5
APCTL1_ADPC6: equ 6 ; ADC Pin Control 6
APCTL1_ADPC7: equ 7 ; ADC Pin Control 7
; bit position masks
mAPCTL1_ADPC0: equ %00000001
mAPCTL1_ADPC1: equ %00000010
mAPCTL1_ADPC2: equ %00000100
mAPCTL1_ADPC3: equ %00001000
mAPCTL1_ADPC4: equ %00010000
mAPCTL1_ADPC5: equ %00100000
mAPCTL1_ADPC6: equ %01000000
mAPCTL1_ADPC7: equ %10000000
;*** APCTL2 - ADC Pin Control 2 Register; 0x00000018 ***
APCTL2: equ $00000018 ;*** APCTL2 - ADC Pin Control 2 Register; 0x00000018 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL2_ADPC8: equ 0 ; ADC Pin Control 8
APCTL2_ADPC9: equ 1 ; ADC Pin Control 9
APCTL2_ADPC10: equ 2 ; ADC Pin Control 10
APCTL2_ADPC11: equ 3 ; ADC Pin Control 11
APCTL2_ADPC12: equ 4 ; ADC Pin Control 12
APCTL2_ADPC13: equ 5 ; ADC Pin Control 13
APCTL2_ADPC14: equ 6 ; ADC Pin Control 14
APCTL2_ADPC15: equ 7 ; ADC Pin Control 15
; bit position masks
mAPCTL2_ADPC8: equ %00000001
mAPCTL2_ADPC9: equ %00000010
mAPCTL2_ADPC10: equ %00000100
mAPCTL2_ADPC11: equ %00001000
mAPCTL2_ADPC12: equ %00010000
mAPCTL2_ADPC13: equ %00100000
mAPCTL2_ADPC14: equ %01000000
mAPCTL2_ADPC15: equ %10000000
;*** APCTL3 - ADC Pin Control 3 Register; 0x00000019 ***
APCTL3: equ $00000019 ;*** APCTL3 - ADC Pin Control 3 Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL3_ADPC16: equ 0 ; ADC Pin Control 16
APCTL3_ADPC17: equ 1 ; ADC Pin Control 17
APCTL3_ADPC18: equ 2 ; ADC Pin Control 18
APCTL3_ADPC19: equ 3 ; ADC Pin Control 19
APCTL3_ADPC20: equ 4 ; ADC Pin Control 20
APCTL3_ADPC21: equ 5 ; ADC Pin Control 21
APCTL3_ADPC22: equ 6 ; ADC Pin Control 22
APCTL3_ADPC23: equ 7 ; ADC Pin Control 23
; bit position masks
mAPCTL3_ADPC16: equ %00000001
mAPCTL3_ADPC17: equ %00000010
mAPCTL3_ADPC18: equ %00000100
mAPCTL3_ADPC19: equ %00001000
mAPCTL3_ADPC20: equ %00010000
mAPCTL3_ADPC21: equ %00100000
mAPCTL3_ADPC22: equ %01000000
mAPCTL3_ADPC23: equ %10000000
;*** IRQSC - Interrupt Request Status and Control Register; 0x0000001C ***
IRQSC: equ $0000001C ;*** IRQSC - Interrupt Request Status and Control Register; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IRQSC_IRQMOD: equ 0 ; IRQ Detection Mode
IRQSC_IRQIE: equ 1 ; IRQ Interrupt Enable
IRQSC_IRQACK: equ 2 ; IRQ Acknowledge
IRQSC_IRQF: equ 3 ; IRQ Flag
IRQSC_IRQPE: equ 4 ; IRQ Pin Enable
IRQSC_IRQEDG: equ 5 ; Interrupt Request (IRQ) Edge Select
IRQSC_IRQPDD: equ 6 ; Interrupt Request (IRQ) Pull Device Disable
; bit position masks
mIRQSC_IRQMOD: equ %00000001
mIRQSC_IRQIE: equ %00000010
mIRQSC_IRQACK: equ %00000100
mIRQSC_IRQF: equ %00001000
mIRQSC_IRQPE: equ %00010000
mIRQSC_IRQEDG: equ %00100000
mIRQSC_IRQPDD: equ %01000000
;*** TPM1SC - TPM 1 Status and Control Register; 0x00000020 ***
TPM1SC: equ $00000020 ;*** TPM1SC - TPM 1 Status and Control Register; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1SC_PS0: equ 0 ; Prescale Divisor Select Bit 0
TPM1SC_PS1: equ 1 ; Prescale Divisor Select Bit 1
TPM1SC_PS2: equ 2 ; Prescale Divisor Select Bit 2
TPM1SC_CLKSA: equ 3 ; Clock Source Select A
TPM1SC_CLKSB: equ 4 ; Clock Source Select B
TPM1SC_CPWMS: equ 5 ; Center-Aligned PWM Select
TPM1SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable
TPM1SC_TOF: equ 7 ; Timer Overflow Flag
; bit position masks
mTPM1SC_PS0: equ %00000001
mTPM1SC_PS1: equ %00000010
mTPM1SC_PS2: equ %00000100
mTPM1SC_CLKSA: equ %00001000
mTPM1SC_CLKSB: equ %00010000
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -