📄 mc9s08dz60.inc
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PTDD_PTDD2: equ 2 ; Port D Data Register Bit 2
PTDD_PTDD3: equ 3 ; Port D Data Register Bit 3
PTDD_PTDD4: equ 4 ; Port D Data Register Bit 4
PTDD_PTDD5: equ 5 ; Port D Data Register Bit 5
PTDD_PTDD6: equ 6 ; Port D Data Register Bit 6
PTDD_PTDD7: equ 7 ; Port D Data Register Bit 7
; bit position masks
mPTDD_PTDD0: equ %00000001
mPTDD_PTDD1: equ %00000010
mPTDD_PTDD2: equ %00000100
mPTDD_PTDD3: equ %00001000
mPTDD_PTDD4: equ %00010000
mPTDD_PTDD5: equ %00100000
mPTDD_PTDD6: equ %01000000
mPTDD_PTDD7: equ %10000000
;*** PTDDD - Data Direction Register D; 0x00000007 ***
PTDDD: equ $00000007 ;*** PTDDD - Data Direction Register D; 0x00000007 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTDDD_PTDDD0: equ 0 ; Data Direction for Port D Bit 0
PTDDD_PTDDD1: equ 1 ; Data Direction for Port D Bit 1
PTDDD_PTDDD2: equ 2 ; Data Direction for Port D Bit 2
PTDDD_PTDDD3: equ 3 ; Data Direction for Port D Bit 3
PTDDD_PTDDD4: equ 4 ; Data Direction for Port D Bit 4
PTDDD_PTDDD5: equ 5 ; Data Direction for Port D Bit 5
PTDDD_PTDDD6: equ 6 ; Data Direction for Port D Bit 6
PTDDD_PTDDD7: equ 7 ; Data Direction for Port D Bit 7
; bit position masks
mPTDDD_PTDDD0: equ %00000001
mPTDDD_PTDDD1: equ %00000010
mPTDDD_PTDDD2: equ %00000100
mPTDDD_PTDDD3: equ %00001000
mPTDDD_PTDDD4: equ %00010000
mPTDDD_PTDDD5: equ %00100000
mPTDDD_PTDDD6: equ %01000000
mPTDDD_PTDDD7: equ %10000000
;*** PTED - Port E Data Register; 0x00000008 ***
PTED: equ $00000008 ;*** PTED - Port E Data Register; 0x00000008 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTED_PTED0: equ 0 ; Port E Data Register Bit 0
PTED_PTED1: equ 1 ; Port E Data Register Bit 1
PTED_PTED2: equ 2 ; Port E Data Register Bit 2
PTED_PTED3: equ 3 ; Port E Data Register Bit 3
PTED_PTED4: equ 4 ; Port E Data Register Bit 4
PTED_PTED5: equ 5 ; Port E Data Register Bit 5
PTED_PTED6: equ 6 ; Port E Data Register Bit 6
PTED_PTED7: equ 7 ; Port E Data Register Bit 7
; bit position masks
mPTED_PTED0: equ %00000001
mPTED_PTED1: equ %00000010
mPTED_PTED2: equ %00000100
mPTED_PTED3: equ %00001000
mPTED_PTED4: equ %00010000
mPTED_PTED5: equ %00100000
mPTED_PTED6: equ %01000000
mPTED_PTED7: equ %10000000
;*** PTEDD - Data Direction Register E; 0x00000009 ***
PTEDD: equ $00000009 ;*** PTEDD - Data Direction Register E; 0x00000009 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTEDD_PTEDD0: equ 0 ; Data Direction for Port E Bit 0
PTEDD_PTEDD1: equ 1 ; Data Direction for Port E Bit 1
PTEDD_PTEDD2: equ 2 ; Data Direction for Port E Bit 2
PTEDD_PTEDD3: equ 3 ; Data Direction for Port E Bit 3
PTEDD_PTEDD4: equ 4 ; Data Direction for Port E Bit 4
PTEDD_PTEDD5: equ 5 ; Data Direction for Port E Bit 5
PTEDD_PTEDD6: equ 6 ; Data Direction for Port E Bit 6
PTEDD_PTEDD7: equ 7 ; Data Direction for Port E Bit 7
; bit position masks
mPTEDD_PTEDD0: equ %00000001
mPTEDD_PTEDD1: equ %00000010
mPTEDD_PTEDD2: equ %00000100
mPTEDD_PTEDD3: equ %00001000
mPTEDD_PTEDD4: equ %00010000
mPTEDD_PTEDD5: equ %00100000
mPTEDD_PTEDD6: equ %01000000
mPTEDD_PTEDD7: equ %10000000
;*** PTFD - Port F Data Register; 0x0000000A ***
PTFD: equ $0000000A ;*** PTFD - Port F Data Register; 0x0000000A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTFD_PTFD0: equ 0 ; Port F Data Register Bit 0
PTFD_PTFD1: equ 1 ; Port F Data Register Bit 1
PTFD_PTFD2: equ 2 ; Port F Data Register Bit 2
PTFD_PTFD3: equ 3 ; Port F Data Register Bit 3
PTFD_PTFD4: equ 4 ; Port F Data Register Bit 4
PTFD_PTFD5: equ 5 ; Port F Data Register Bit 5
PTFD_PTFD6: equ 6 ; Port F Data Register Bit 6
PTFD_PTFD7: equ 7 ; Port F Data Register Bit 7
; bit position masks
mPTFD_PTFD0: equ %00000001
mPTFD_PTFD1: equ %00000010
mPTFD_PTFD2: equ %00000100
mPTFD_PTFD3: equ %00001000
mPTFD_PTFD4: equ %00010000
mPTFD_PTFD5: equ %00100000
mPTFD_PTFD6: equ %01000000
mPTFD_PTFD7: equ %10000000
;*** PTFDD - Data Direction Register F; 0x0000000B ***
PTFDD: equ $0000000B ;*** PTFDD - Data Direction Register F; 0x0000000B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTFDD_PTFDD0: equ 0 ; Data Direction for Port F Bit 0
PTFDD_PTFDD1: equ 1 ; Data Direction for Port F Bit 1
PTFDD_PTFDD2: equ 2 ; Data Direction for Port F Bit 2
PTFDD_PTFDD3: equ 3 ; Data Direction for Port F Bit 3
PTFDD_PTFDD4: equ 4 ; Data Direction for Port F Bit 4
PTFDD_PTFDD5: equ 5 ; Data Direction for Port F Bit 5
PTFDD_PTFDD6: equ 6 ; Data Direction for Port F Bit 6
PTFDD_PTFDD7: equ 7 ; Data Direction for Port F Bit 7
; bit position masks
mPTFDD_PTFDD0: equ %00000001
mPTFDD_PTFDD1: equ %00000010
mPTFDD_PTFDD2: equ %00000100
mPTFDD_PTFDD3: equ %00001000
mPTFDD_PTFDD4: equ %00010000
mPTFDD_PTFDD5: equ %00100000
mPTFDD_PTFDD6: equ %01000000
mPTFDD_PTFDD7: equ %10000000
;*** PTGD - Port G Data Register; 0x0000000C ***
PTGD: equ $0000000C ;*** PTGD - Port G Data Register; 0x0000000C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTGD_PTGD0: equ 0 ; Port G Data Register Bit 0
PTGD_PTGD1: equ 1 ; Port G Data Register Bit 1
PTGD_PTGD2: equ 2 ; Port G Data Register Bit 2
PTGD_PTGD3: equ 3 ; Port G Data Register Bit 3
PTGD_PTGD4: equ 4 ; Port G Data Register Bit 4
PTGD_PTGD5: equ 5 ; Port G Data Register Bit 5
; bit position masks
mPTGD_PTGD0: equ %00000001
mPTGD_PTGD1: equ %00000010
mPTGD_PTGD2: equ %00000100
mPTGD_PTGD3: equ %00001000
mPTGD_PTGD4: equ %00010000
mPTGD_PTGD5: equ %00100000
;*** PTGDD - Data Direction Register G; 0x0000000D ***
PTGDD: equ $0000000D ;*** PTGDD - Data Direction Register G; 0x0000000D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTGDD_PTGDD0: equ 0 ; Data Direction for Port G Bit 0
PTGDD_PTGDD1: equ 1 ; Data Direction for Port G Bit 1
PTGDD_PTGDD2: equ 2 ; Data Direction for Port G Bit 2
PTGDD_PTGDD3: equ 3 ; Data Direction for Port G Bit 3
PTGDD_PTGDD4: equ 4 ; Data Direction for Port G Bit 4
PTGDD_PTGDD5: equ 5 ; Data Direction for Port G Bit 5
; bit position masks
mPTGDD_PTGDD0: equ %00000001
mPTGDD_PTGDD1: equ %00000010
mPTGDD_PTGDD2: equ %00000100
mPTGDD_PTGDD3: equ %00001000
mPTGDD_PTGDD4: equ %00010000
mPTGDD_PTGDD5: equ %00100000
;*** ACMP1SC - Analog Comparator 1 Status and Control Register; 0x0000000E ***
ACMP1SC: equ $0000000E ;*** ACMP1SC - Analog Comparator 1 Status and Control Register; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP1SC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMP1SC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMP1SC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMP1SC_ACO: equ 3 ; Analog Comparator Output
ACMP1SC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMP1SC_ACF: equ 5 ; Analog Comparator Flag
ACMP1SC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMP1SC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMP1SC_ACMOD0: equ %00000001
mACMP1SC_ACMOD1: equ %00000010
mACMP1SC_ACOPE: equ %00000100
mACMP1SC_ACO: equ %00001000
mACMP1SC_ACIE: equ %00010000
mACMP1SC_ACF: equ %00100000
mACMP1SC_ACBGS: equ %01000000
mACMP1SC_ACME: equ %10000000
;*** ACMP2SC - Analog Comparator 2 Status and Control Register; 0x0000000F ***
ACMP2SC: equ $0000000F ;*** ACMP2SC - Analog Comparator 2 Status and Control Register; 0x0000000F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP2SC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMP2SC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMP2SC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMP2SC_ACO: equ 3 ; Analog Comparator Output
ACMP2SC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMP2SC_ACF: equ 5 ; Analog Comparator Flag
ACMP2SC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMP2SC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMP2SC_ACMOD0: equ %00000001
mACMP2SC_ACMOD1: equ %00000010
mACMP2SC_ACOPE: equ %00000100
mACMP2SC_ACO: equ %00001000
mACMP2SC_ACIE: equ %00010000
mACMP2SC_ACF: equ %00100000
mACMP2SC_ACBGS: equ %01000000
mACMP2SC_ACME: equ %10000000
;*** ADSC1 - Status and Control Register; 0x00000010 ***
ADSC1: equ $00000010 ;*** ADSC1 - Status and Control Register; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADSC1_ADCH0: equ 0 ; Input Channel Select Bit 0
ADSC1_ADCH1: equ 1 ; Input Channel Select Bit 1
ADSC1_ADCH2: equ 2 ; Input Channel Select Bit 2
ADSC1_ADCH3: equ 3 ; Input Channel Select Bit 3
ADSC1_ADCH4: equ 4 ; Input Channel Select Bit 4
ADSC1_ADCO: equ 5 ; Continuous Conversion Enable
ADSC1_AIEN: equ 6 ; Interrupt Enable
ADSC1_COCO: equ 7 ; Conversion Complete Flag
; bit position masks
mADSC1_ADCH0: equ %00000001
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