📄 mc9s08dz60.inc
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; Based on CPU DB MC9S08DZ60_64, version 2.87.006 (RegistersPrg V2.03)
; ###################################################################
; Filename : MC9S08DZ60.inc
; Processor : MC9S08DZ60FEE
; FileFormat: V2.03
; DataSheet : MC9S08DZ60 Rev. 0.05 8/5/2005
; Compiler : CodeWarrior compiler
; Date/Time : 13.02.2006, 16:03
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 14.11.2005, V2.00 :
; - Deprecated symbols added for backward compatibility (section at the end of this file)
; - 15.11.2005, V2.01 :
; - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family.
; - 17.12.2005, V2.02 :
; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
; - 16.01.2006, V2.03 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
;
; CPU Registers Revisions:
; - none
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $00001900
ROMEnd: equ $0000FFAF
Z_RAMStart: equ $00000080
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $0000107F
ROM1Start: equ $00001080
ROM1End: equ $000013FF
EEPROMStart: equ $00001400
EEPROMEnd: equ $000017FF
;
Vacmp2: equ $0000FFC0
Vacmp1: equ $0000FFC2
Vcantx: equ $0000FFC4
Vcanrx: equ $0000FFC6
Vcanerr: equ $0000FFC8
Vcanwu: equ $0000FFCA
Vrtc: equ $0000FFCC
Viic: equ $0000FFCE
Vadc: equ $0000FFD0
Vport: equ $0000FFD2
Vsci2tx: equ $0000FFD4
Vsci2rx: equ $0000FFD6
Vsci2err: equ $0000FFD8
Vsci1tx: equ $0000FFDA
Vsci1rx: equ $0000FFDC
Vsci1err: equ $0000FFDE
Vspi1: equ $0000FFE0
Vtpm2ovf: equ $0000FFE2
Vtpm2ch1: equ $0000FFE4
Vtpm2ch0: equ $0000FFE6
Vtpm1ovf: equ $0000FFE8
Vtpm1ch5: equ $0000FFEA
Vtpm1ch4: equ $0000FFEC
Vtpm1ch3: equ $0000FFEE
Vtpm1ch2: equ $0000FFF0
Vtpm1ch1: equ $0000FFF2
Vtpm1ch0: equ $0000FFF4
Vlol: equ $0000FFF6
Vlvd: equ $0000FFF8
Virq: equ $0000FFFA
Vswi: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PTAD - Port A Data Register; 0x00000000 ***
PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0
PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1
PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2
PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3
PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4
PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5
PTAD_PTAD6: equ 6 ; Port A Data Register Bit 6
PTAD_PTAD7: equ 7 ; Port A Data Register Bit 7
; bit position masks
mPTAD_PTAD0: equ %00000001
mPTAD_PTAD1: equ %00000010
mPTAD_PTAD2: equ %00000100
mPTAD_PTAD3: equ %00001000
mPTAD_PTAD4: equ %00010000
mPTAD_PTAD5: equ %00100000
mPTAD_PTAD6: equ %01000000
mPTAD_PTAD7: equ %10000000
;*** PTADD - Data Direction Register A; 0x00000001 ***
PTADD: equ $00000001 ;*** PTADD - Data Direction Register A; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0
PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1
PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2
PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3
PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4
PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5
PTADD_PTADD6: equ 6 ; Data Direction for Port A Bit 6
PTADD_PTADD7: equ 7 ; Data Direction for Port A Bit 7
; bit position masks
mPTADD_PTADD0: equ %00000001
mPTADD_PTADD1: equ %00000010
mPTADD_PTADD2: equ %00000100
mPTADD_PTADD3: equ %00001000
mPTADD_PTADD4: equ %00010000
mPTADD_PTADD5: equ %00100000
mPTADD_PTADD6: equ %01000000
mPTADD_PTADD7: equ %10000000
;*** PTBD - Port B Data Register; 0x00000002 ***
PTBD: equ $00000002 ;*** PTBD - Port B Data Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBD_PTBD0: equ 0 ; Port B Data Register Bit 0
PTBD_PTBD1: equ 1 ; Port B Data Register Bit 1
PTBD_PTBD2: equ 2 ; Port B Data Register Bit 2
PTBD_PTBD3: equ 3 ; Port B Data Register Bit 3
PTBD_PTBD4: equ 4 ; Port B Data Register Bit 4
PTBD_PTBD5: equ 5 ; Port B Data Register Bit 5
PTBD_PTBD6: equ 6 ; Port B Data Register Bit 6
PTBD_PTBD7: equ 7 ; Port B Data Register Bit 7
; bit position masks
mPTBD_PTBD0: equ %00000001
mPTBD_PTBD1: equ %00000010
mPTBD_PTBD2: equ %00000100
mPTBD_PTBD3: equ %00001000
mPTBD_PTBD4: equ %00010000
mPTBD_PTBD5: equ %00100000
mPTBD_PTBD6: equ %01000000
mPTBD_PTBD7: equ %10000000
;*** PTBDD - Data Direction Register B; 0x00000003 ***
PTBDD: equ $00000003 ;*** PTBDD - Data Direction Register B; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBDD_PTBDD0: equ 0 ; Data Direction for Port B Bit 0
PTBDD_PTBDD1: equ 1 ; Data Direction for Port B Bit 1
PTBDD_PTBDD2: equ 2 ; Data Direction for Port B Bit 2
PTBDD_PTBDD3: equ 3 ; Data Direction for Port B Bit 3
PTBDD_PTBDD4: equ 4 ; Data Direction for Port B Bit 4
PTBDD_PTBDD5: equ 5 ; Data Direction for Port B Bit 5
PTBDD_PTBDD6: equ 6 ; Data Direction for Port B Bit 6
PTBDD_PTBDD7: equ 7 ; Data Direction for Port B Bit 7
; bit position masks
mPTBDD_PTBDD0: equ %00000001
mPTBDD_PTBDD1: equ %00000010
mPTBDD_PTBDD2: equ %00000100
mPTBDD_PTBDD3: equ %00001000
mPTBDD_PTBDD4: equ %00010000
mPTBDD_PTBDD5: equ %00100000
mPTBDD_PTBDD6: equ %01000000
mPTBDD_PTBDD7: equ %10000000
;*** PTCD - Port C Data Register; 0x00000004 ***
PTCD: equ $00000004 ;*** PTCD - Port C Data Register; 0x00000004 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTCD_PTCD0: equ 0 ; Port C Data Register Bit 0
PTCD_PTCD1: equ 1 ; Port C Data Register Bit 1
PTCD_PTCD2: equ 2 ; Port C Data Register Bit 2
PTCD_PTCD3: equ 3 ; Port C Data Register Bit 3
PTCD_PTCD4: equ 4 ; Port C Data Register Bit 4
PTCD_PTCD5: equ 5 ; Port C Data Register Bit 5
PTCD_PTCD6: equ 6 ; Port C Data Register Bit 6
PTCD_PTCD7: equ 7 ; Port C Data Register Bit 7
; bit position masks
mPTCD_PTCD0: equ %00000001
mPTCD_PTCD1: equ %00000010
mPTCD_PTCD2: equ %00000100
mPTCD_PTCD3: equ %00001000
mPTCD_PTCD4: equ %00010000
mPTCD_PTCD5: equ %00100000
mPTCD_PTCD6: equ %01000000
mPTCD_PTCD7: equ %10000000
;*** PTCDD - Data Direction Register C; 0x00000005 ***
PTCDD: equ $00000005 ;*** PTCDD - Data Direction Register C; 0x00000005 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTCDD_PTCDD0: equ 0 ; Data Direction for Port C Bit 0
PTCDD_PTCDD1: equ 1 ; Data Direction for Port C Bit 1
PTCDD_PTCDD2: equ 2 ; Data Direction for Port C Bit 2
PTCDD_PTCDD3: equ 3 ; Data Direction for Port C Bit 3
PTCDD_PTCDD4: equ 4 ; Data Direction for Port C Bit 4
PTCDD_PTCDD5: equ 5 ; Data Direction for Port C Bit 5
PTCDD_PTCDD6: equ 6 ; Data Direction for Port C Bit 6
PTCDD_PTCDD7: equ 7 ; Data Direction for Port C Bit 7
; bit position masks
mPTCDD_PTCDD0: equ %00000001
mPTCDD_PTCDD1: equ %00000010
mPTCDD_PTCDD2: equ %00000100
mPTCDD_PTCDD3: equ %00001000
mPTCDD_PTCDD4: equ %00010000
mPTCDD_PTCDD5: equ %00100000
mPTCDD_PTCDD6: equ %01000000
mPTCDD_PTCDD7: equ %10000000
;*** PTDD - Port D Data Register; 0x00000006 ***
PTDD: equ $00000006 ;*** PTDD - Port D Data Register; 0x00000006 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTDD_PTDD0: equ 0 ; Port D Data Register Bit 0
PTDD_PTDD1: equ 1 ; Port D Data Register Bit 1
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