📄 slfprgr-jk3.asm
字号:
;*********************************************************************
; HEADER_START
;
; $File Name: slfprgR-jk3.asm$
; Project: Developper's HC08 Bootloader Slave
; Description: JK/JL main bootloader file
; Platform: HC08
; $Version: 6.0.22.0$
; $Date: Feb-22-2006$
; $Last Modified By: r30323$
; Company: Freescale Semiconductor
; Security: General Business
;
; ===================================================================
; Copyright (c): Freescale Semiconductor, 2004, All rights reserved.
;
; ===================================================================
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END
include "reg-jk3.h"
RCS_ENA EQU 0 ; READ COMMAND SUPPORTED?
IFNE RCS_ENA
RCS EQU $80 ; READ COMMAND SUPPORTED
ELSE
RCS EQU 0 ; READ COMMAND unSUPPORTED
ENDIF
VER_NUM EQU 1 ; FC protocol version number
ERBLK_LEN EQU 64
WRBLK_LEN EQU 32
FLS_END EQU $FA80 ; this is APL_VECT address (also from PRM file)
INT_VECT EQU $FFDC
FLBPRMASK EQU $E000 ; this is CPU specific FLBPR mask (i.e. bits that are always in the address)
ROMSTART EQU $FC00
GETBYTE EQU ROMSTART+0
RDVRRNG EQU ROMSTART+3
ERARNGE EQU ROMSTART+6
PRGRNGE EQU ROMSTART+9
DELNUS EQU ROMSTART+12
RAMSTART EQU $80
CTRLBYT EQU RAMSTART+$08
CPUSPD EQU RAMSTART+$09
LADDR EQU RAMSTART+$0A
DATA EQU RAMSTART+$0C
Jx1_FLS_BEG EQU $F600 ; flash start for Jx1
Jx3_FLS_BEG EQU $EC00 ; flash start for Jx3
;**************************************************************************
IF PLATFORM = 1
FLS_BEG EQU Jx3_FLS_BEG ; JK3 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTD ; <<<
TXDPIN EQU 4 ; <<<
SCITXINV EQU 0 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 0 ; (if RXD uses IRQ pin instead)
RXDPORT EQU PTD ; <<<
RXDPIN EQU 5 ; <<<
RXDPUEN EQU 1 ; use pull-up feature
BUSCLOCK EQU 1228800 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 6 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 2
FLS_BEG EQU Jx3_FLS_BEG ; JK3 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTD ; <<<
TXDPIN EQU 5 ; <<<
SCITXINV EQU 1 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 1 ; (if RXD uses IRQ pin instead)
RXDPUEN EQU 0 ; undefine pull-up enabling port
BUSCLOCK EQU 1228800 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 6 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 3
FLS_BEG EQU Jx3_FLS_BEG ; JK3 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTD ; <<<
TXDPIN EQU 5 ; <<<
SCITXINV EQU 1 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 1 ; (if RXD uses IRQ pin instead)
RXDPUEN EQU 0 ; don't use pull-up feature
BUSCLOCK EQU 4000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 19200
CALENABLED EQU 0 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 16 ; specify BUS*4 clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 4
FLS_BEG EQU Jx3_FLS_BEG ; JK3 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTD ; <<<
TXDPIN EQU 6 ; <<<
SCITXINV EQU 1 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 1 ; (if RXD uses IRQ pin instead)
RXDPUEN EQU 0 ; undefine pull-up enabling port
BUSCLOCK EQU 4000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 19200
CALENABLED EQU 0 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 16 ; specify BUS*4 clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 5
FLS_BEG EQU Jx3_FLS_BEG ; JK3 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTD ; <<<
TXDPIN EQU 1 ; <<<
SCITXINV EQU 0 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 0 ; (if RXD uses IRQ pin instead)
IF RXDISIRQ = 0 ; RXDPORT & RXDPIN is defined
RXDPORT EQU PTA ; <<<
RXDPIN EQU 4 ; <<<
RXDPUEN EQU 1 ; use pull-up feature
ENDIF
BUSCLOCK EQU 2000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 10 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 6
FLS_BEG EQU Jx3_FLS_BEG ; JK1 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTB ; <<<
TXDPIN EQU 4 ; <<<
SCITXINV EQU 0 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 0 ; (if RXD uses IRQ pin instead)
IF RXDISIRQ = 0 ; RXDPORT & RXDPIN is defined
RXDPORT EQU PTB ; <<<
RXDPIN EQU 3 ; <<<
RXDPUEN EQU 0 ; use pull-up feature
ENDIF
BUSCLOCK EQU 2000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 10 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 7
FLS_BEG EQU Jx3_FLS_BEG ; JK1 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTA ; <<<
TXDPIN EQU 1 ; <<<
SCITXINV EQU 0 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 0 ; (if RXD uses IRQ pin instead)
IF RXDISIRQ = 0 ; RXDPORT & RXDPIN is defined
RXDPORT EQU PTA ; <<<
RXDPIN EQU 0 ; <<<
RXDPUEN EQU 1 ; use pull-up feature
ENDIF
BUSCLOCK EQU 2000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 10 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
IF PLATFORM = 8
FLS_BEG EQU Jx3_FLS_BEG ; JK1 used
IDENTS MACRO
DC.B 'J3',0 ; soft SCI
ENDM
TXDPORT EQU PTA ; <<<
TXDPIN EQU 1 ; <<<
SCITXINV EQU 0 ; (1 if SCI TX is inverted (no drivers))
SCIRXINV EQU SCITXINV ; (1 if SCI RX is inverted (no drivers))
RXDISIRQ EQU 0 ; (if RXD uses IRQ pin instead)
IF RXDISIRQ = 0 ; RXDPORT & RXDPIN is defined
RXDPORT EQU PTA ; <<<
RXDPIN EQU 1 ; <<<
RXDPUEN EQU 1 ; use pull-up feature
ENDIF
BUSCLOCK EQU 2000000 ; <<< MODIFY SO IT IS NEAR YOUR BUS CLOCK!
SCISPEED EQU 9600
CALENABLED EQU 1 ; calibration enabled
IF CALENABLED = 0
SPEED EQU 10 ; specify Xtal clk in MHz if no calibration (known freq.)
ENDIF
ENDIF
;**************************************************************************
;**************************************************************************
IF RXDISIRQ = 1 ; RXDPORT & RXDPIN is *not* defined
IF SCIRXINV = 1
CONFIG2DEF EQU %10000000 ; pullup on IRQ disabled! you need hardwired pull-down in fact!
ELSE
CONFIG2DEF EQU %00000000 ; pullup on IRQ enabled!
ENDIF
ELSE
CONFIG2DEF EQU %00000000 ; pullup on IRQ *not* disabled!
RXDDDR EQU RXDPORT+4
IF RXDPUEN = 1
RXDPUE EQU RXDPORT+$0B ; define pull-up enable port
ENDIF
ENDIF
TXDDDR EQU TXDPORT+4
SCITXTICK EQU (BUSCLOCK/SCISPEED)
;**************************************************************************
IF RXDISIRQ = 0 ; RXDPORT & RXDPIN is defined
IF (RXDPORT = TXDPORT) & (RXDPIN = TXDPIN)
SINGLEWIRE EQU 1 ; do use single-wire feature
ELSE
SINGLEWIRE EQU 0 ; do NOT use single-wire feature
ENDIF
ELSE
SINGLEWIRE EQU 0 ; do NOT use single-wire feature
ENDIF
;*******************************************************************************************
XDEF main
XDEF VEC1
XDEF VEC2
XDEF VEC3
XDEF VEC4
XDEF VEC5
XDEF VEC6
XDEF VEC7
XDEF VEC8
XDEF VEC9
XDEF VEC10
XDEF VEC11
XDEF VEC12
XDEF VEC13
XDEF VEC14
XDEF VEC15
XDEF VEC16
XDEF SCIAPIREF
XDEF FLBPR
WR_DATA EQU 'W'
RD_DATA EQU 'R'
ENDPRG EQU 'Q'
ERASE EQU 'E'
ACK EQU $FC
IDENT EQU 'I'
T100MS EQU 255
ILOP MACRO
DC.B $32 ; this is illegal operation code
ENDM
SKIP1 MACRO
DC.B $21 ; BRANCH NEVER (saves memory)
ENDM
SKIP2 MACRO
DC.B $65 ; CPHX (saves memory)
ENDM
BRRXDLO MACRO
IF RXDISIRQ = 1
IF SCIRXINV = 1
BIH \1 ; branch if RXD low
ELSE
BIL \1 ; branch if RXD low
ENDIF
ELSE ; RXD uses normal I/O pin
IF SCIRXINV = 1
BRSET RXDPIN,RXDPORT,\1 ; branch if RXD low
ELSE
BRCLR RXDPIN,RXDPORT,\1 ; branch if RXD low
ENDIF
ENDIF
ENDM
BRRXDHI MACRO
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -