mc9s08qd4.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

TPM2MODL_BIT0:      equ    0                                         ; Timer Counter Modulo Bit 0
TPM2MODL_BIT1:      equ    1                                         ; Timer Counter Modulo Bit 1
TPM2MODL_BIT2:      equ    2                                         ; Timer Counter Modulo Bit 2
TPM2MODL_BIT3:      equ    3                                         ; Timer Counter Modulo Bit 3
TPM2MODL_BIT4:      equ    4                                         ; Timer Counter Modulo Bit 4
TPM2MODL_BIT5:      equ    5                                         ; Timer Counter Modulo Bit 5
TPM2MODL_BIT6:      equ    6                                         ; Timer Counter Modulo Bit 6
TPM2MODL_BIT7:      equ    7                                         ; Timer Counter Modulo Bit 7
; bit position masks
mTPM2MODL_BIT0:     equ    %00000001
mTPM2MODL_BIT1:     equ    %00000010
mTPM2MODL_BIT2:     equ    %00000100
mTPM2MODL_BIT3:     equ    %00001000
mTPM2MODL_BIT4:     equ    %00010000
mTPM2MODL_BIT5:     equ    %00100000
mTPM2MODL_BIT6:     equ    %01000000
mTPM2MODL_BIT7:     equ    %10000000


;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000025 ***
TPM2C0SC:           equ    $00000025                                ;*** TPM2C0SC - TPM2 Timer Channel 0 Status and Control Register; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2C0SC_ELS0A:     equ    2                                         ; Edge/Level Select Bit A
TPM2C0SC_ELS0B:     equ    3                                         ; Edge/Level Select Bit B
TPM2C0SC_MS0A:      equ    4                                         ; Mode Select A for TPM Channel 0
TPM2C0SC_MS0B:      equ    5                                         ; Mode Select B for TPM Channel 0
TPM2C0SC_CH0IE:     equ    6                                         ; Channel 0 Interrupt Enable
TPM2C0SC_CH0F:      equ    7                                         ; Channel 0 Flag
; bit position masks
mTPM2C0SC_ELS0A:    equ    %00000100
mTPM2C0SC_ELS0B:    equ    %00001000
mTPM2C0SC_MS0A:     equ    %00010000
mTPM2C0SC_MS0B:     equ    %00100000
mTPM2C0SC_CH0IE:    equ    %01000000
mTPM2C0SC_CH0F:     equ    %10000000


;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000026 ***
TPM2C0V:            equ    $00000026                                ;*** TPM2C0V - TPM2 Timer Channel 0 Value Register; 0x00000026 ***


;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000026 ***
TPM2C0VH:           equ    $00000026                                ;*** TPM2C0VH - TPM2 Timer Channel 0 Value Register High; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2C0VH_BIT8:      equ    0                                         ; Timer Channel 0 Value Bit 8
TPM2C0VH_BIT9:      equ    1                                         ; Timer Channel 0 Value Bit 9
TPM2C0VH_BIT10:     equ    2                                         ; Timer Channel 0 Value Bit 10
TPM2C0VH_BIT11:     equ    3                                         ; Timer Channel 0 Value Bit 11
TPM2C0VH_BIT12:     equ    4                                         ; Timer Channel 0 Value Bit 12
TPM2C0VH_BIT13:     equ    5                                         ; Timer Channel 0 Value Bit 13
TPM2C0VH_BIT14:     equ    6                                         ; Timer Channel 0 Value Bit 14
TPM2C0VH_BIT15:     equ    7                                         ; Timer Channel 0 Value Bit 15
; bit position masks
mTPM2C0VH_BIT8:     equ    %00000001
mTPM2C0VH_BIT9:     equ    %00000010
mTPM2C0VH_BIT10:    equ    %00000100
mTPM2C0VH_BIT11:    equ    %00001000
mTPM2C0VH_BIT12:    equ    %00010000
mTPM2C0VH_BIT13:    equ    %00100000
mTPM2C0VH_BIT14:    equ    %01000000
mTPM2C0VH_BIT15:    equ    %10000000


;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000027 ***
TPM2C0VL:           equ    $00000027                                ;*** TPM2C0VL - TPM2 Timer Channel 0 Value Register Low; 0x00000027 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2C0VL_BIT0:      equ    0                                         ; Timer Channel 0 Value Bit 0
TPM2C0VL_BIT1:      equ    1                                         ; Timer Channel 0 Value Bit 1
TPM2C0VL_BIT2:      equ    2                                         ; Timer Channel 0 Value Bit 2
TPM2C0VL_BIT3:      equ    3                                         ; Timer Channel 0 Value Bit 3
TPM2C0VL_BIT4:      equ    4                                         ; Timer Channel 0 Value Bit 4
TPM2C0VL_BIT5:      equ    5                                         ; Timer Channel 0 Value Bit 5
TPM2C0VL_BIT6:      equ    6                                         ; Timer Channel 0 Value Bit 6
TPM2C0VL_BIT7:      equ    7                                         ; Timer Channel 0 Value Bit 7
; bit position masks
mTPM2C0VL_BIT0:     equ    %00000001
mTPM2C0VL_BIT1:     equ    %00000010
mTPM2C0VL_BIT2:     equ    %00000100
mTPM2C0VL_BIT3:     equ    %00001000
mTPM2C0VL_BIT4:     equ    %00010000
mTPM2C0VL_BIT5:     equ    %00100000
mTPM2C0VL_BIT6:     equ    %01000000
mTPM2C0VL_BIT7:     equ    %10000000


;*** ICSC1 - ICS Control Register 1; 0x00000038 ***
ICSC1:              equ    $00000038                                ;*** ICSC1 - ICS Control Register 1; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC1_IREFSTEN:     equ    0                                         ; Internal Reference Stop Enable
ICSC1_CLKS:         equ    6                                         ; Clock Source Select
; bit position masks
mICSC1_IREFSTEN:    equ    %00000001
mICSC1_CLKS:        equ    %01000000


;*** ICSC2 - ICS Control Register 2; 0x00000039 ***
ICSC2:              equ    $00000039                                ;*** ICSC2 - ICS Control Register 2; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC2_LP:           equ    3                                         ; Low Power Select
ICSC2_BDIV0:        equ    6                                         ; Bus Frequency Divider, bit 0
ICSC2_BDIV1:        equ    7                                         ; Bus Frequency Divider, bit 1
; bit position masks
mICSC2_LP:          equ    %00001000
mICSC2_BDIV0:       equ    %01000000
mICSC2_BDIV1:       equ    %10000000


;*** ICSTRM - ICS Trim Register; 0x0000003A ***
ICSTRM:             equ    $0000003A                                ;*** ICSTRM - ICS Trim Register; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSTRM_TRIM0:       equ    0                                         ; ICS Trim Setting, bit 0
ICSTRM_TRIM1:       equ    1                                         ; ICS Trim Setting, bit 1
ICSTRM_TRIM2:       equ    2                                         ; ICS Trim Setting, bit 2
ICSTRM_TRIM3:       equ    3                                         ; ICS Trim Setting, bit 3
ICSTRM_TRIM4:       equ    4                                         ; ICS Trim Setting, bit 4
ICSTRM_TRIM5:       equ    5                                         ; ICS Trim Setting, bit 5
ICSTRM_TRIM6:       equ    6                                         ; ICS Trim Setting, bit 6
ICSTRM_TRIM7:       equ    7                                         ; ICS Trim Setting, bit 7
; bit position masks
mICSTRM_TRIM0:      equ    %00000001
mICSTRM_TRIM1:      equ    %00000010
mICSTRM_TRIM2:      equ    %00000100
mICSTRM_TRIM3:      equ    %00001000
mICSTRM_TRIM4:      equ    %00010000
mICSTRM_TRIM5:      equ    %00100000
mICSTRM_TRIM6:      equ    %01000000
mICSTRM_TRIM7:      equ    %10000000


;*** ICSSC - ICS Status and Control; 0x0000003B ***
ICSSC:              equ    $0000003B                                ;*** ICSSC - ICS Status and Control; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSSC_FTRIM:        equ    0                                         ; ICS Fine Trim
ICSSC_CLKST:        equ    2                                         ; Clock Mode Status
; bit position masks
mICSSC_FTRIM:       equ    %00000001
mICSSC_CLKST:       equ    %00000100


;*** TPMSC - TPM Timer Status and Control Register; 0x00000040 ***
TPMSC:              equ    $00000040                                ;*** TPMSC - TPM Timer Status and Control Register; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPMSC_PS0:          equ    0                                         ; Prescale Divisor Select Bit 0
TPMSC_PS1:          equ    1                                         ; Prescale Divisor Select Bit 1
TPMSC_PS2:          equ    2                                         ; Prescale Divisor Select Bit 2
TPMSC_CLKSA:        equ    3                                         ; Clock Source Select A
TPMSC_CLKSB:        equ    4                                         ; Clock Source Select B
TPMSC_CPWMS:        equ    5                                         ; Center-Aligned PWM Select
TPMSC_TOIE:         equ    6                                         ; Timer Overflow Interrupt Enable
TPMSC_TOF:          equ    7                                         ; Timer Overflow Flag
; bit position masks
mTPMSC_PS0:         equ    %00000001
mTPMSC_PS1:         equ    %00000010
mTPMSC_PS2:         equ    %00000100
mTPMSC_CLKSA:       equ    %00001000
mTPMSC_CLKSB:       equ    %00010000
mTPMSC_CPWMS:       equ    %00100000
mTPMSC_TOIE:        equ    %01000000
mTPMSC_TOF:         equ    %10000000


;*** TPMCNT - TPM Counter Register; 0x00000041 ***
TPMCNT:             equ    $00000041                                ;*** TPMCNT - TPM Counter Register; 0x00000041 ***


;*** TPMCNTH - TPM Counter Register High; 0x00000041 ***
TPMCNTH:            equ    $00000041                                ;*** TPMCNTH - TPM Counter Register High; 0x00000041 ***


;*** TPMCNTL - TPM Counter Register Low; 0x00000042 ***
TPMCNTL:            equ    $00000042                                ;*** TPMCNTL - TPM Counter Register Low; 0x00000042 ***


;*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000043 ***
TPMMOD:             equ    $00000043                                ;*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000043 ***


;*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000043 ***
TPMMODH:            equ    $00000043                                ;*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000043 ***


;*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000044 ***
TPMMODL:            equ    $00000044                                ;*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000044 ***


;*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000045 ***
TPMC0SC:            equ    $00000045                                ;*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000045 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPMC0SC_ELS0A:      equ    2                                         ; Edge/Level Select Bit A
TPMC0SC_ELS0B:      equ    3                                         ; Edge/Level Select Bit B
TPMC0SC_MS0A:       equ    4                                         ; Mode Select A for TPM Channel 0
TPMC0SC_MS0B:       equ    5                                         ; Mode Select B for TPM Channel 0
TPMC0SC_CH0IE:      equ    6                                         ; Channel 0 Interrupt Enable
TPMC0SC_CH0F:       equ    7                                         ; Channel 0 Flag
; bit position masks
mTPMC0SC_ELS0A:     equ    %00000100
mTPMC0SC_ELS0B:     equ    %00001000
mTPMC0SC_MS0A:      equ    %00010000
mTPMC0SC_MS0B:      equ    %00100000
mTPMC0SC_CH0IE:     equ    %01000000
mTPMC0SC_CH0F:      equ    %10000000


;*** TPMC0V - TPM Timer Channel 0 Value Register; 0x00000046 ***
TPMC0V:             equ    $00000046                                ;*** TPMC0V - TPM Timer Channel 0 Value Register; 0x00000046 ***


;*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0x00000046 ***
TPMC0VH:            equ    $00000046                                ;*** TPMC0VH - TPM Timer Channel 0 Value Register High; 0x00000046 ***


;*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0x00000047 ***
TPMC0VL:            equ    $00000047                                ;*** TPMC0VL - TPM Timer Channel 0 Value Register Low; 0x00000047 ***


;*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0x00000048 ***
TPMC1SC:            equ    $00000048                                ;*** TPMC1SC - TPM Timer Channel 1 Status and Control Register; 0x00000048 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPMC1SC_ELS1A:      equ    2                                         ; Edge/Level Select Bit A
TPMC1SC_ELS1B:      equ    3                                         ; Edge/Level Select Bit B