mc9s08qd4.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

ADC1SC2:            equ    $00000011                                ;*** ADC1SC2 - Status and Control Register 2; 0x00000011 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1SC2_ACFGT:      equ    4                                         ; Compare Function Greater Than Enable
ADC1SC2_ACFE:       equ    5                                         ; Compare Function Enable
ADC1SC2_ADTRG:      equ    6                                         ; Conversion Trigger Select
ADC1SC2_ADACT:      equ    7                                         ; Conversion Active
; bit position masks
mADC1SC2_ACFGT:     equ    %00010000
mADC1SC2_ACFE:      equ    %00100000
mADC1SC2_ADTRG:     equ    %01000000
mADC1SC2_ADACT:     equ    %10000000


;*** ADC1R - ADC10 Result Data Right Justified; 0x00000012 ***
ADC1R:              equ    $00000012                                ;*** ADC1R - ADC10 Result Data Right Justified; 0x00000012 ***


;*** ADC1RH - ADC10 Result Data Right Justified High; 0x00000012 ***
ADC1RH:             equ    $00000012                                ;*** ADC1RH - ADC10 Result Data Right Justified High; 0x00000012 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1RH_ADR8:        equ    0                                         ; ADC10 Result Data Bit 8
ADC1RH_ADR9:        equ    1                                         ; ADC10 Result Data Bit 9
; bit position masks
mADC1RH_ADR8:       equ    %00000001
mADC1RH_ADR9:       equ    %00000010


;*** ADC1RL - ADC10 Result Data Right Justified Low; 0x00000013 ***
ADC1RL:             equ    $00000013                                ;*** ADC1RL - ADC10 Result Data Right Justified Low; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1RL_ADR0:        equ    0                                         ; ADC10 Result Data Bit 0
ADC1RL_ADR1:        equ    1                                         ; ADC10 Result Data Bit 1
ADC1RL_ADR2:        equ    2                                         ; ADC10 Result Data Bit 2
ADC1RL_ADR3:        equ    3                                         ; ADC10 Result Data Bit 3
ADC1RL_ADR4:        equ    4                                         ; ADC10 Result Data Bit 4
ADC1RL_ADR5:        equ    5                                         ; ADC10 Result Data Bit 5
ADC1RL_ADR6:        equ    6                                         ; ADC10 Result Data Bit 6
ADC1RL_ADR7:        equ    7                                         ; ADC10 Result Data Bit 7
; bit position masks
mADC1RL_ADR0:       equ    %00000001
mADC1RL_ADR1:       equ    %00000010
mADC1RL_ADR2:       equ    %00000100
mADC1RL_ADR3:       equ    %00001000
mADC1RL_ADR4:       equ    %00010000
mADC1RL_ADR5:       equ    %00100000
mADC1RL_ADR6:       equ    %01000000
mADC1RL_ADR7:       equ    %10000000


;*** ADC1CV - Compare Value Register; 0x00000014 ***
ADC1CV:             equ    $00000014                                ;*** ADC1CV - Compare Value Register; 0x00000014 ***


;*** ADC1CVH - Compare Value Register High; 0x00000014 ***
ADC1CVH:            equ    $00000014                                ;*** ADC1CVH - Compare Value Register High; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1CVH_ADCV8:      equ    0                                         ; Compare Function Value 8
ADC1CVH_ADCV9:      equ    1                                         ; Compare Function Value 9
; bit position masks
mADC1CVH_ADCV8:     equ    %00000001
mADC1CVH_ADCV9:     equ    %00000010


;*** ADC1CVL - Compare Value Register Low; 0x00000015 ***
ADC1CVL:            equ    $00000015                                ;*** ADC1CVL - Compare Value Register Low; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1CVL_ADCV0:      equ    0                                         ; Compare Function Value 0
ADC1CVL_ADCV1:      equ    1                                         ; Compare Function Value 1
ADC1CVL_ADCV2:      equ    2                                         ; Compare Function Value 2
ADC1CVL_ADCV3:      equ    3                                         ; Compare Function Value 3
ADC1CVL_ADCV4:      equ    4                                         ; Compare Function Value 4
ADC1CVL_ADCV5:      equ    5                                         ; Compare Function Value 5
ADC1CVL_ADCV6:      equ    6                                         ; Compare Function Value 6
ADC1CVL_ADCV7:      equ    7                                         ; Compare Function Value 7
; bit position masks
mADC1CVL_ADCV0:     equ    %00000001
mADC1CVL_ADCV1:     equ    %00000010
mADC1CVL_ADCV2:     equ    %00000100
mADC1CVL_ADCV3:     equ    %00001000
mADC1CVL_ADCV4:     equ    %00010000
mADC1CVL_ADCV5:     equ    %00100000
mADC1CVL_ADCV6:     equ    %01000000
mADC1CVL_ADCV7:     equ    %10000000


;*** ADC1CFG - Configuration Register; 0x00000016 ***
ADC1CFG:            equ    $00000016                                ;*** ADC1CFG - Configuration Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1CFG_ADICLK0:    equ    0                                         ; Input Clock Select Bit 0
ADC1CFG_ADICLK1:    equ    1                                         ; Input Clock Select Bit 1
ADC1CFG_MODE0:      equ    2                                         ; Conversion Mode Selection Bit 0
ADC1CFG_MODE1:      equ    3                                         ; Conversion Mode Selection Bit 1
ADC1CFG_ADLSMP:     equ    4                                         ; Long Sample Time Configuration
ADC1CFG_ADIV0:      equ    5                                         ; Clock Divide Select Bit 0
ADC1CFG_ADIV1:      equ    6                                         ; Clock Divide Select Bit 1
ADC1CFG_ADLPC:      equ    7                                         ; Low Power Configuration
; bit position masks
mADC1CFG_ADICLK0:   equ    %00000001
mADC1CFG_ADICLK1:   equ    %00000010
mADC1CFG_MODE0:     equ    %00000100
mADC1CFG_MODE1:     equ    %00001000
mADC1CFG_ADLSMP:    equ    %00010000
mADC1CFG_ADIV0:     equ    %00100000
mADC1CFG_ADIV1:     equ    %01000000
mADC1CFG_ADLPC:     equ    %10000000


;*** APCTL1 - ADC10 Pin Control 1 Register; 0x00000017 ***
APCTL1:             equ    $00000017                                ;*** APCTL1 - ADC10 Pin Control 1 Register; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL1_ADPC0:       equ    0                                         ; ADC10 Pin Control 0
APCTL1_ADPC1:       equ    1                                         ; ADC10 Pin Control 1
APCTL1_ADPC2:       equ    2                                         ; ADC10 Pin Control 2
APCTL1_ADPC3:       equ    3                                         ; ADC10 Pin Control 3
; bit position masks
mAPCTL1_ADPC0:      equ    %00000001
mAPCTL1_ADPC1:      equ    %00000010
mAPCTL1_ADPC2:      equ    %00000100
mAPCTL1_ADPC3:      equ    %00001000


;*** TPM2SC - TPM2 Timer Status and Control Register; 0x00000020 ***
TPM2SC:             equ    $00000020                                ;*** TPM2SC - TPM2 Timer Status and Control Register; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2SC_PS0:         equ    0                                         ; Prescale Divisor Select Bit 0
TPM2SC_PS1:         equ    1                                         ; Prescale Divisor Select Bit 1
TPM2SC_PS2:         equ    2                                         ; Prescale Divisor Select Bit 2
TPM2SC_CLKSA:       equ    3                                         ; Clock Source Select A
TPM2SC_CLKSB:       equ    4                                         ; Clock Source Select B
TPM2SC_CPWMS:       equ    5                                         ; Center-Aligned PWM Select
TPM2SC_TOIE:        equ    6                                         ; Timer Overflow Interrupt Enable
TPM2SC_TOF:         equ    7                                         ; Timer Overflow Flag
; bit position masks
mTPM2SC_PS0:        equ    %00000001
mTPM2SC_PS1:        equ    %00000010
mTPM2SC_PS2:        equ    %00000100
mTPM2SC_CLKSA:      equ    %00001000
mTPM2SC_CLKSB:      equ    %00010000
mTPM2SC_CPWMS:      equ    %00100000
mTPM2SC_TOIE:       equ    %01000000
mTPM2SC_TOF:        equ    %10000000


;*** TPM2CNT - TPM2 Counter Register; 0x00000021 ***
TPM2CNT:            equ    $00000021                                ;*** TPM2CNT - TPM2 Counter Register; 0x00000021 ***


;*** TPM2CNTH - TPM2 Counter Register High; 0x00000021 ***
TPM2CNTH:           equ    $00000021                                ;*** TPM2CNTH - TPM2 Counter Register High; 0x00000021 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2CNTH_BIT8:      equ    0                                         ; TPM2 Counter Bit 8
TPM2CNTH_BIT9:      equ    1                                         ; TPM2 Counter Bit 9
TPM2CNTH_BIT10:     equ    2                                         ; TPM2 Counter Bit 10
TPM2CNTH_BIT11:     equ    3                                         ; TPM2 Counter Bit 11
TPM2CNTH_BIT12:     equ    4                                         ; TPM2 Counter Bit 12
TPM2CNTH_BIT13:     equ    5                                         ; TPM2 Counter Bit 13
TPM2CNTH_BIT14:     equ    6                                         ; TPM2 Counter Bit 14
TPM2CNTH_BIT15:     equ    7                                         ; TPM2 Counter Bit 15
; bit position masks
mTPM2CNTH_BIT8:     equ    %00000001
mTPM2CNTH_BIT9:     equ    %00000010
mTPM2CNTH_BIT10:    equ    %00000100
mTPM2CNTH_BIT11:    equ    %00001000
mTPM2CNTH_BIT12:    equ    %00010000
mTPM2CNTH_BIT13:    equ    %00100000
mTPM2CNTH_BIT14:    equ    %01000000
mTPM2CNTH_BIT15:    equ    %10000000


;*** TPM2CNTL - TPM2 Counter Register Low; 0x00000022 ***
TPM2CNTL:           equ    $00000022                                ;*** TPM2CNTL - TPM2 Counter Register Low; 0x00000022 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2CNTL_BIT0:      equ    0                                         ; TPM2 Counter Bit 0
TPM2CNTL_BIT1:      equ    1                                         ; TPM2 Counter Bit 1
TPM2CNTL_BIT2:      equ    2                                         ; TPM2 Counter Bit 2
TPM2CNTL_BIT3:      equ    3                                         ; TPM2 Counter Bit 3
TPM2CNTL_BIT4:      equ    4                                         ; TPM2 Counter Bit 4
TPM2CNTL_BIT5:      equ    5                                         ; TPM2 Counter Bit 5
TPM2CNTL_BIT6:      equ    6                                         ; TPM2 Counter Bit 6
TPM2CNTL_BIT7:      equ    7                                         ; TPM2 Counter Bit 7
; bit position masks
mTPM2CNTL_BIT0:     equ    %00000001
mTPM2CNTL_BIT1:     equ    %00000010
mTPM2CNTL_BIT2:     equ    %00000100
mTPM2CNTL_BIT3:     equ    %00001000
mTPM2CNTL_BIT4:     equ    %00010000
mTPM2CNTL_BIT5:     equ    %00100000
mTPM2CNTL_BIT6:     equ    %01000000
mTPM2CNTL_BIT7:     equ    %10000000


;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000023 ***
TPM2MOD:            equ    $00000023                                ;*** TPM2MOD - TPM2 Timer Counter Modulo Register; 0x00000023 ***


;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000023 ***
TPM2MODH:           equ    $00000023                                ;*** TPM2MODH - TPM2 Timer Counter Modulo Register High; 0x00000023 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM2MODH_BIT8:      equ    0                                         ; Timer Counter Modulo Bit 8
TPM2MODH_BIT9:      equ    1                                         ; Timer Counter Modulo Bit 9
TPM2MODH_BIT10:     equ    2                                         ; Timer Counter Modulo Bit 10
TPM2MODH_BIT11:     equ    3                                         ; Timer Counter Modulo Bit 11
TPM2MODH_BIT12:     equ    4                                         ; Timer Counter Modulo Bit 12
TPM2MODH_BIT13:     equ    5                                         ; Timer Counter Modulo Bit 13
TPM2MODH_BIT14:     equ    6                                         ; Timer Counter Modulo Bit 14
TPM2MODH_BIT15:     equ    7                                         ; Timer Counter Modulo Bit 15
; bit position masks
mTPM2MODH_BIT8:     equ    %00000001
mTPM2MODH_BIT9:     equ    %00000010
mTPM2MODH_BIT10:    equ    %00000100
mTPM2MODH_BIT11:    equ    %00001000
mTPM2MODH_BIT12:    equ    %00010000
mTPM2MODH_BIT13:    equ    %00100000
mTPM2MODH_BIT14:    equ    %01000000
mTPM2MODH_BIT15:    equ    %10000000


;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000024 ***
TPM2MODL:           equ    $00000024                                ;*** TPM2MODL - TPM2 Timer Counter Modulo Register Low; 0x00000024 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET