📄 mc9s08qd4.inc
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; Based on CPU DB MC9S08QD4_8, version 2.87.007 (RegistersPrg V2.08)
; ###################################################################
; Filename : mc9s08qd4.inc
; Processor : MC9S08QD4VEDE
; FileFormat: V2.08
; DataSheet : MC9S08QD4 Rev. 0.8 26/6/2006
; Compiler : CodeWarrior compiler
; Date/Time : 11.07.2006, 14:48
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 14.11.2005, V2.00 :
; - Deprecated symbols added for backward compatibility (section at the end of this file)
; - 15.11.2005, V2.01 :
; - Revision is not related to this file (CPU family)
; - 17.12.2005, V2.02 :
; - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
; - 16.01.2006, V2.03 :
; - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
; - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
; - 08.03.2006, V2.04 :
; - Support for bit(s) names duplicated with any register name in .h header files
; - 24.03.2006, V2.05 :
; - Revision is not related to this file (CPU family)
; - 26.04.2006, V2.06 :
; - Absolute assembly supported (depreciated symbols are not defined)
; - 27.04.2006, V2.07 :
; - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
; - 07.06.2006, V2.08 :
; - For .inc files added constants "RAMStart" and "RAMEnd" even there is only Z_RAM.
;
; CPU Registers Revisions:
; - none
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $0000F000
ROMEnd: equ $0000FFAD
Z_RAMStart: equ $00000060
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $0000015F
ROM1Start: equ $0000FFC0
ROM1End: equ $0000FFCF
;
Vrti: equ $0000FFD0
Reserved1: equ $0000FFD2
Reserved2: equ $0000FFD4
Reserved3: equ $0000FFD6
Vadc1: equ $0000FFD8
Vkeyboard1: equ $0000FFDA
Reserved6: equ $0000FFDC
Reserved7: equ $0000FFDE
Reserved8: equ $0000FFE0
Reserved9: equ $0000FFE2
Reserved10: equ $0000FFE4
Reserved11: equ $0000FFE6
Reserved12: equ $0000FFE8
Vtpm2ovf: equ $0000FFEA
Reserved14: equ $0000FFEC
Vtpm2ch0: equ $0000FFEE
Vtpm1ovf: equ $0000FFF0
Vtpm1ch1: equ $0000FFF2
Vtpm1ch0: equ $0000FFF4
Reserved19: equ $0000FFF6
Virq: equ $0000FFF8
Vlvd: equ $0000FFFA
Vswi: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PTAD - Port A Data Register; 0x00000000 ***
PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0
PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1
PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2
PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3
PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4
PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5
; bit position masks
mPTAD_PTAD0: equ %00000001
mPTAD_PTAD1: equ %00000010
mPTAD_PTAD2: equ %00000100
mPTAD_PTAD3: equ %00001000
mPTAD_PTAD4: equ %00010000
mPTAD_PTAD5: equ %00100000
;*** PTADD - Data Direction Register A; 0x00000001 ***
PTADD: equ $00000001 ;*** PTADD - Data Direction Register A; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0
PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1
PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2
PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3
PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4
PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5
; bit position masks
mPTADD_PTADD0: equ %00000001
mPTADD_PTADD1: equ %00000010
mPTADD_PTADD2: equ %00000100
mPTADD_PTADD3: equ %00001000
mPTADD_PTADD4: equ %00010000
mPTADD_PTADD5: equ %00100000
;*** KBISC - KBI Status and Control; 0x0000000C ***
KBISC: equ $0000000C ;*** KBISC - KBI Status and Control; 0x0000000C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBISC_KBIMOD: equ 0 ; Keyboard Detection Mode
KBISC_KBIE: equ 1 ; Keyboard Interrupt Enable
KBISC_KBACK: equ 2 ; Keyboard Interrupt Acknowledge
KBISC_KBF: equ 3 ; Keyboard Interrupt Flag
; bit position masks
mKBISC_KBIMOD: equ %00000001
mKBISC_KBIE: equ %00000010
mKBISC_KBACK: equ %00000100
mKBISC_KBF: equ %00001000
;*** KBIPE - KBI Pin Enable Register; 0x0000000D ***
KBIPE: equ $0000000D ;*** KBIPE - KBI Pin Enable Register; 0x0000000D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBIPE_KBIPE0: equ 0 ; Keyboard Pin Enable for Port A Bit 0
KBIPE_KBIPE1: equ 1 ; Keyboard Pin Enable for Port A Bit 1
KBIPE_KBIPE2: equ 2 ; Keyboard Pin Enable for Port A Bit 2
KBIPE_KBIPE3: equ 3 ; Keyboard Pin Enable for Port A Bit 3
KBIPE_KBIPE4: equ 4 ; Keyboard Pin Enable for Port A Bit 4
KBIPE_KBIPE5: equ 5 ; Keyboard Pin Enable for Port A Bit 5
KBIPE_KBIPE6: equ 6 ; Keyboard Pin Enable for Port A Bit 6
KBIPE_KBIPE7: equ 7 ; Keyboard Pin Enable for Port A Bit 7
; bit position masks
mKBIPE_KBIPE0: equ %00000001
mKBIPE_KBIPE1: equ %00000010
mKBIPE_KBIPE2: equ %00000100
mKBIPE_KBIPE3: equ %00001000
mKBIPE_KBIPE4: equ %00010000
mKBIPE_KBIPE5: equ %00100000
mKBIPE_KBIPE6: equ %01000000
mKBIPE_KBIPE7: equ %10000000
;*** KBIES - KBI Edge Select Register; 0x0000000E ***
KBIES: equ $0000000E ;*** KBIES - KBI Edge Select Register; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBIES_KBEDG0: equ 0 ; Keyboard Edge Select Bit 0
KBIES_KBEDG1: equ 1 ; Keyboard Edge Select Bit 1
KBIES_KBEDG2: equ 2 ; Keyboard Edge Select Bit 2
KBIES_KBEDG3: equ 3 ; Keyboard Edge Select Bit 3
KBIES_KBEDG4: equ 4 ; Keyboard Edge Select Bit 4
KBIES_KBEDG5: equ 5 ; Keyboard Edge Select Bit 5
KBIES_KBEDG6: equ 6 ; Keyboard Edge Select Bit 6
KBIES_KBEDG7: equ 7 ; Keyboard Edge Select Bit 7
; bit position masks
mKBIES_KBEDG0: equ %00000001
mKBIES_KBEDG1: equ %00000010
mKBIES_KBEDG2: equ %00000100
mKBIES_KBEDG3: equ %00001000
mKBIES_KBEDG4: equ %00010000
mKBIES_KBEDG5: equ %00100000
mKBIES_KBEDG6: equ %01000000
mKBIES_KBEDG7: equ %10000000
;*** IRQSC - Interrupt Request Status and Control Register; 0x0000000F ***
IRQSC: equ $0000000F ;*** IRQSC - Interrupt Request Status and Control Register; 0x0000000F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IRQSC_IRQMOD: equ 0 ; IRQ Detection Mode
IRQSC_IRQIE: equ 1 ; IRQ Interrupt Enable
IRQSC_IRQACK: equ 2 ; IRQ Acknowledge
IRQSC_IRQF: equ 3 ; IRQ Flag
IRQSC_IRQPE: equ 4 ; IRQ Pin Enable
IRQSC_IRQEDG: equ 5 ; Interrupt Request (IRQ) Edge Select
IRQSC_IRQPDD: equ 6 ; Interrupt Request (IRQ) Pull Device Disable
; bit position masks
mIRQSC_IRQMOD: equ %00000001
mIRQSC_IRQIE: equ %00000010
mIRQSC_IRQACK: equ %00000100
mIRQSC_IRQF: equ %00001000
mIRQSC_IRQPE: equ %00010000
mIRQSC_IRQEDG: equ %00100000
mIRQSC_IRQPDD: equ %01000000
;*** ADC1SC1 - Status and Control Register; 0x00000010 ***
ADC1SC1: equ $00000010 ;*** ADC1SC1 - Status and Control Register; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADC1SC1_ADCH0: equ 0 ; Input Channel Select Bit 0
ADC1SC1_ADCH1: equ 1 ; Input Channel Select Bit 1
ADC1SC1_ADCH2: equ 2 ; Input Channel Select Bit 2
ADC1SC1_ADCH3: equ 3 ; Input Channel Select Bit 3
ADC1SC1_ADCH4: equ 4 ; Input Channel Select Bit 4
ADC1SC1_ADCO: equ 5 ; Continuous Conversion Enable
ADC1SC1_AIEN: equ 6 ; Interrupt Enable
ADC1SC1_COCO: equ 7 ; Conversion Complete Flag
; bit position masks
mADC1SC1_ADCH0: equ %00000001
mADC1SC1_ADCH1: equ %00000010
mADC1SC1_ADCH2: equ %00000100
mADC1SC1_ADCH3: equ %00001000
mADC1SC1_ADCH4: equ %00010000
mADC1SC1_ADCO: equ %00100000
mADC1SC1_AIEN: equ %01000000
mADC1SC1_COCO: equ %10000000
;*** ADC1SC2 - Status and Control Register 2; 0x00000011 ***
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