mc9s08lc60.inc
来自「M68HC08及HCS08系列单片机bootloader引导程序源码/示例」· INC 代码 · 共 1,122 行 · 第 1/5 页
INC
1,122 行
mSPI2C2_SPC0: equ %00000001
mSPI2C2_SPISWAI: equ %00000010
mSPI2C2_BIDIROE: equ %00001000
mSPI2C2_MODFEN: equ %00010000
;*** SPI2BR - SPI2 Baud Rate Register; 0x00000032 ***
SPI2BR: equ $00000032 ;*** SPI2BR - SPI2 Baud Rate Register; 0x00000032 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI2BR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPI2BR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPI2BR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPI2BR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPI2BR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPI2BR_SPPR2: equ 6 ; SP1 Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPI2BR_SPR0: equ %00000001
mSPI2BR_SPR1: equ %00000010
mSPI2BR_SPR2: equ %00000100
mSPI2BR_SPPR0: equ %00010000
mSPI2BR_SPPR1: equ %00100000
mSPI2BR_SPPR2: equ %01000000
;*** SPI2S - SPI2 Status Register; 0x00000033 ***
SPI2S: equ $00000033 ;*** SPI2S - SPI2 Status Register; 0x00000033 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI2S_MODF: equ 4 ; Master Mode Fault Flag
SPI2S_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPI2S_SPRF: equ 7 ; SP1 Read Buffer Full Flag
; bit position masks
mSPI2S_MODF: equ %00010000
mSPI2S_SPTEF: equ %00100000
mSPI2S_SPRF: equ %10000000
;*** SPI2D - SPI2 Data Register; 0x00000035 ***
SPI2D: equ $00000035 ;*** SPI2D - SPI2 Data Register; 0x00000035 ***
;*** ICGC1 - ICG Control Register 1; 0x00000038 ***
ICGC1: equ $00000038 ;*** ICGC1 - ICG Control Register 1; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGC1_LOCD: equ 1 ; Loss of Clock Disable
ICGC1_OSCSTEN: equ 2 ; Enable Oscillator in Off Mode
ICGC1_CLKS0: equ 3 ; Clock Mode Select Bit 0
ICGC1_CLKS1: equ 4 ; Clock Mode Select Bit 1
ICGC1_REFS: equ 5 ; External Reference Select
ICGC1_RANGE: equ 6 ; Frequency Range Select
ICGC1_HGO: equ 7 ; High Gain Oscillator Select
; bit position masks
mICGC1_LOCD: equ %00000010
mICGC1_OSCSTEN: equ %00000100
mICGC1_CLKS0: equ %00001000
mICGC1_CLKS1: equ %00010000
mICGC1_REFS: equ %00100000
mICGC1_RANGE: equ %01000000
mICGC1_HGO: equ %10000000
;*** ICGC2 - ICG Control Register 2; 0x00000039 ***
ICGC2: equ $00000039 ;*** ICGC2 - ICG Control Register 2; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGC2_RFD0: equ 0 ; Reduced Frequency Divider Bit 0
ICGC2_RFD1: equ 1 ; Reduced Frequency Divider Bit 1
ICGC2_RFD2: equ 2 ; Reduced Frequency Divider Bit 2
ICGC2_LOCRE: equ 3 ; Loss of Clock Reset Enable
ICGC2_MFD0: equ 4 ; Multiplication Factor Bit 0
ICGC2_MFD1: equ 5 ; Multiplication Factor Bit 1
ICGC2_MFD2: equ 6 ; Multiplication Factor Bit 2
ICGC2_LOLRE: equ 7 ; Loss of Lock Reset Enable
; bit position masks
mICGC2_RFD0: equ %00000001
mICGC2_RFD1: equ %00000010
mICGC2_RFD2: equ %00000100
mICGC2_LOCRE: equ %00001000
mICGC2_MFD0: equ %00010000
mICGC2_MFD1: equ %00100000
mICGC2_MFD2: equ %01000000
mICGC2_LOLRE: equ %10000000
;*** ICGS1 - ICG Status Register 1; 0x0000003A ***
ICGS1: equ $0000003A ;*** ICGS1 - ICG Status Register 1; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGS1_ICGIF: equ 0 ; ICG Interrupt Flag
ICGS1_ERCS: equ 1 ; External Reference Clock Status
ICGS1_LOCS: equ 2 ; Loss Of Clock Status
ICGS1_LOCK: equ 3 ; FLL Lock Status
ICGS1_LOLS: equ 4 ; FLL Loss of Lock Status
ICGS1_REFST: equ 5 ; Reference Clock Status
ICGS1_CLKST0: equ 6 ; Clock Mode Status Bit 0
ICGS1_CLKST1: equ 7 ; Clock Mode Status Bit 1
; bit position masks
mICGS1_ICGIF: equ %00000001
mICGS1_ERCS: equ %00000010
mICGS1_LOCS: equ %00000100
mICGS1_LOCK: equ %00001000
mICGS1_LOLS: equ %00010000
mICGS1_REFST: equ %00100000
mICGS1_CLKST0: equ %01000000
mICGS1_CLKST1: equ %10000000
;*** ICGS2 - ICG Status Register 2; 0x0000003B ***
ICGS2: equ $0000003B ;*** ICGS2 - ICG Status Register 2; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGS2_DCOS: equ 0 ; DCO Clock Stable
; bit position masks
mICGS2_DCOS: equ %00000001
;*** ICGFLT - ICG Upper Filter; 0x0000003C ***
ICGFLT: equ $0000003C ;*** ICGFLT - ICG Upper Filter; 0x0000003C ***
;*** ICGFLTU - ICG Upper Filter Register; 0x0000003C ***
ICGFLTU: equ $0000003C ;*** ICGFLTU - ICG Upper Filter Register; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGFLTU_FILT8: equ 0 ; ICG Filter Bit 8
ICGFLTU_FILT9: equ 1 ; ICG Filter Bit 9
ICGFLTU_FILT10: equ 2 ; ICG Filter Bit 10
ICGFLTU_FILT11: equ 3 ; ICG Filter Bit 11
; bit position masks
mICGFLTU_FILT8: equ %00000001
mICGFLTU_FILT9: equ %00000010
mICGFLTU_FILT10: equ %00000100
mICGFLTU_FILT11: equ %00001000
;*** ICGFLTL - ICG Lower Filter Register; 0x0000003D ***
ICGFLTL: equ $0000003D ;*** ICGFLTL - ICG Lower Filter Register; 0x0000003D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGFLTL_FILT0: equ 0 ; ICG Filter Bit 0
ICGFLTL_FILT1: equ 1 ; ICG Filter Bit 1
ICGFLTL_FILT2: equ 2 ; ICG Filter Bit 2
ICGFLTL_FILT3: equ 3 ; ICG Filter Bit 3
ICGFLTL_FILT4: equ 4 ; ICG Filter Bit 4
ICGFLTL_FILT5: equ 5 ; ICG Filter Bit 5
ICGFLTL_FILT6: equ 6 ; ICG Filter Bit 6
ICGFLTL_FILT7: equ 7 ; ICG Filter Bit 7
; bit position masks
mICGFLTL_FILT0: equ %00000001
mICGFLTL_FILT1: equ %00000010
mICGFLTL_FILT2: equ %00000100
mICGFLTL_FILT3: equ %00001000
mICGFLTL_FILT4: equ %00010000
mICGFLTL_FILT5: equ %00100000
mICGFLTL_FILT6: equ %01000000
mICGFLTL_FILT7: equ %10000000
;*** ICGTRM - ICG Trim Register; 0x0000003E ***
ICGTRM: equ $0000003E ;*** ICGTRM - ICG Trim Register; 0x0000003E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICGTRM_TRIM0: equ 0 ; ICG Trim Bit 0
ICGTRM_TRIM1: equ 1 ; ICG Trim Bit 1
ICGTRM_TRIM2: equ 2 ; ICG Trim Bit 2
ICGTRM_TRIM3: equ 3 ; ICG Trim Bit 3
ICGTRM_TRIM4: equ 4 ; ICG Trim Bit 4
ICGTRM_TRIM5: equ 5 ; ICG Trim Bit 5
ICGTRM_TRIM6: equ 6 ; ICG Trim Bit 6
ICGTRM_TRIM7: equ 7 ; ICG Trim Bit 7
; bit position masks
mICGTRM_TRIM0: equ %00000001
mICGTRM_TRIM1: equ %00000010
mICGTRM_TRIM2: equ %00000100
mICGTRM_TRIM3: equ %00001000
mICGTRM_TRIM4: equ %00010000
mICGTRM_TRIM5: equ %00100000
mICGTRM_TRIM6: equ %01000000
mICGTRM_TRIM7: equ %10000000
;*** TPM1SC - TPM 1 Status and Control Register; 0x00000040 ***
TPM1SC: equ $00000040 ;*** TPM1SC - TPM 1 Status and Control Register; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1SC_PS0: equ 0 ; Prescale Divisor Select Bit 0
TPM1SC_PS1: equ 1 ; Prescale Divisor Select Bit 1
TPM1SC_PS2: equ 2 ; Prescale Divisor Select Bit 2
TPM1SC_CLKSA: equ 3 ; Clock Source Select A
TPM1SC_CLKSB: equ 4 ; Clock Source Select B
TPM1SC_CPWMS: equ 5 ; Center-Aligned PWM Select
TPM1SC_TOIE: equ 6 ; Timer Overflow Interrupt Enable
TPM1SC_TOF: equ 7 ; Timer Overflow Flag
; bit position masks
mTPM1SC_PS0: equ %00000001
mTPM1SC_PS1: equ %00000010
mTPM1SC_PS2: equ %00000100
mTPM1SC_CLKSA: equ %00001000
mTPM1SC_CLKSB: equ %00010000
mTPM1SC_CPWMS: equ %00100000
mTPM1SC_TOIE: equ %01000000
mTPM1SC_TOF: equ %10000000
;*** TPM1CNT - TPM 1 Counter Register; 0x00000041 ***
TPM1CNT: equ $00000041 ;*** TPM1CNT - TPM 1 Counter Register; 0x00000041 ***
;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000041 ***
TPM1CNTH: equ $00000041 ;*** TPM1CNTH - TPM 1 Counter Register High; 0x00000041 ***
;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000042 ***
TPM1CNTL: equ $00000042 ;*** TPM1CNTL - TPM 1 Counter Register Low; 0x00000042 ***
;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000043 ***
TPM1MOD: equ $00000043 ;*** TPM1MOD - TPM 1 Timer Counter Modulo Register; 0x00000043 ***
;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000043 ***
TPM1MODH: equ $00000043 ;*** TPM1MODH - TPM 1 Timer Counter Modulo Register High; 0x00000043 ***
;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000044 ***
TPM1MODL: equ $00000044 ;*** TPM1MODL - TPM 1 Timer Counter Modulo Register Low; 0x00000044 ***
;*** TPM1C0SC - TPM 1 Timer Channel 0 Status and Control Register; 0x00000045 ***
TPM1C0SC: equ $00000045 ;*** TPM1C0SC - TPM 1 Timer Channel 0 St⌨️ 快捷键说明
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