📄 mc9s08lc60.inc
字号:
mSCIBDL_SBR5: equ %00100000
mSCIBDL_SBR6: equ %01000000
mSCIBDL_SBR7: equ %10000000
;*** SCIC1 - SCI Control Register 1; 0x00000022 ***
SCIC1: equ $00000022 ;*** SCIC1 - SCI Control Register 1; 0x00000022 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC1_PT: equ 0 ; Parity Type
SCIC1_PE: equ 1 ; Parity Enable
SCIC1_ILT: equ 2 ; Idle Line Type Select
SCIC1_WAKE: equ 3 ; Receiver Wakeup Method Select
SCIC1_M: equ 4 ; 9-Bit or 8-Bit Mode Select
SCIC1_RSRC: equ 5 ; Receiver Source Select
SCIC1_SCISWAI: equ 6 ; SCI Stops in Wait Mode
SCIC1_LOOPS: equ 7 ; Loop Mode Select
; bit position masks
mSCIC1_PT: equ %00000001
mSCIC1_PE: equ %00000010
mSCIC1_ILT: equ %00000100
mSCIC1_WAKE: equ %00001000
mSCIC1_M: equ %00010000
mSCIC1_RSRC: equ %00100000
mSCIC1_SCISWAI: equ %01000000
mSCIC1_LOOPS: equ %10000000
;*** SCIC2 - SCI Control Register 2; 0x00000023 ***
SCIC2: equ $00000023 ;*** SCIC2 - SCI Control Register 2; 0x00000023 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC2_SBK: equ 0 ; Send Break
SCIC2_RWU: equ 1 ; Receiver Wakeup Control
SCIC2_RE: equ 2 ; Receiver Enable
SCIC2_TE: equ 3 ; Transmitter Enable
SCIC2_ILIE: equ 4 ; Idle Line Interrupt Enable (for IDLE)
SCIC2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF)
SCIC2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC)
SCIC2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE)
; bit position masks
mSCIC2_SBK: equ %00000001
mSCIC2_RWU: equ %00000010
mSCIC2_RE: equ %00000100
mSCIC2_TE: equ %00001000
mSCIC2_ILIE: equ %00010000
mSCIC2_RIE: equ %00100000
mSCIC2_TCIE: equ %01000000
mSCIC2_TIE: equ %10000000
;*** SCIS1 - SCI Status Register 1; 0x00000024 ***
SCIS1: equ $00000024 ;*** SCIS1 - SCI Status Register 1; 0x00000024 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIS1_PF: equ 0 ; Parity Error Flag
SCIS1_FE: equ 1 ; Framing Error Flag
SCIS1_NF: equ 2 ; Noise Flag
SCIS1_OR: equ 3 ; Receiver Overrun Flag
SCIS1_IDLE: equ 4 ; Idle Line Flag
SCIS1_RDRF: equ 5 ; Receive Data Register Full Flag
SCIS1_TC: equ 6 ; Transmission Complete Flag
SCIS1_TDRE: equ 7 ; Transmit Data Register Empty Flag
; bit position masks
mSCIS1_PF: equ %00000001
mSCIS1_FE: equ %00000010
mSCIS1_NF: equ %00000100
mSCIS1_OR: equ %00001000
mSCIS1_IDLE: equ %00010000
mSCIS1_RDRF: equ %00100000
mSCIS1_TC: equ %01000000
mSCIS1_TDRE: equ %10000000
;*** SCIS2 - SCI Status Register 2; 0x00000025 ***
SCIS2: equ $00000025 ;*** SCIS2 - SCI Status Register 2; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIS2_RAF: equ 0 ; Receiver Active Flag
SCIS2_BRK13: equ 2 ; Break Character Length
; bit position masks
mSCIS2_RAF: equ %00000001
mSCIS2_BRK13: equ %00000100
;*** SCIC3 - SCI Control Register 3; 0x00000026 ***
SCIC3: equ $00000026 ;*** SCIC3 - SCI Control Register 3; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC3_PEIE: equ 0 ; Parity Error Interrupt Enable
SCIC3_FEIE: equ 1 ; Framing Error Interrupt Enable
SCIC3_NEIE: equ 2 ; Noise Error Interrupt Enable
SCIC3_ORIE: equ 3 ; Overrun Interrupt Enable
SCIC3_TXINV: equ 4 ; Transmit Data Inversion
SCIC3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode
SCIC3_T8: equ 6 ; Ninth Data Bit for Transmitter
SCIC3_R8: equ 7 ; Ninth Data Bit for Receiver
; bit position masks
mSCIC3_PEIE: equ %00000001
mSCIC3_FEIE: equ %00000010
mSCIC3_NEIE: equ %00000100
mSCIC3_ORIE: equ %00001000
mSCIC3_TXINV: equ %00010000
mSCIC3_TXDIR: equ %00100000
mSCIC3_T8: equ %01000000
mSCIC3_R8: equ %10000000
;*** SCID - SCI Data Register; 0x00000027 ***
SCID: equ $00000027 ;*** SCID - SCI Data Register; 0x00000027 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCID_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCID_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCID_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCID_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCID_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCID_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCID_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCID_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCID_R0_T0: equ %00000001
mSCID_R1_T1: equ %00000010
mSCID_R2_T2: equ %00000100
mSCID_R3_T3: equ %00001000
mSCID_R4_T4: equ %00010000
mSCID_R5_T5: equ %00100000
mSCID_R6_T6: equ %01000000
mSCID_R7_T7: equ %10000000
;*** SPI1C1 - SPI1 Control Register 1; 0x00000028 ***
SPI1C1: equ $00000028 ;*** SPI1C1 - SPI1 Control Register 1; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1C1_LSBFE: equ 0 ; LSB First (shifter direction)
SPI1C1_SSOE: equ 1 ; Slave Select Output Enable
SPI1C1_CPHA: equ 2 ; Clock Phase
SPI1C1_CPOL: equ 3 ; Clock Polarity
SPI1C1_MSTR: equ 4 ; Master/Slave Mode Select
SPI1C1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable
SPI1C1_SPE: equ 6 ; SPI System Enable
SPI1C1_SPIE: equ 7 ; SPI Interrupt Enable
; bit position masks
mSPI1C1_LSBFE: equ %00000001
mSPI1C1_SSOE: equ %00000010
mSPI1C1_CPHA: equ %00000100
mSPI1C1_CPOL: equ %00001000
mSPI1C1_MSTR: equ %00010000
mSPI1C1_SPTIE: equ %00100000
mSPI1C1_SPE: equ %01000000
mSPI1C1_SPIE: equ %10000000
;*** SPI1C2 - SPI1 Control Register 2; 0x00000029 ***
SPI1C2: equ $00000029 ;*** SPI1C2 - SPI1 Control Register 2; 0x00000029 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1C2_SPC0: equ 0 ; SPI Pin Control 0
SPI1C2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPI1C2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPI1C2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
mSPI1C2_SPC0: equ %00000001
mSPI1C2_SPISWAI: equ %00000010
mSPI1C2_BIDIROE: equ %00001000
mSPI1C2_MODFEN: equ %00010000
;*** SPI1BR - SPI1 Baud Rate Register; 0x0000002A ***
SPI1BR: equ $0000002A ;*** SPI1BR - SPI1 Baud Rate Register; 0x0000002A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1BR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPI1BR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPI1BR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPI1BR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPI1BR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPI1BR_SPPR2: equ 6 ; SP1 Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPI1BR_SPR0: equ %00000001
mSPI1BR_SPR1: equ %00000010
mSPI1BR_SPR2: equ %00000100
mSPI1BR_SPPR0: equ %00010000
mSPI1BR_SPPR1: equ %00100000
mSPI1BR_SPPR2: equ %01000000
;*** SPI1S - SPI1 Status Register; 0x0000002B ***
SPI1S: equ $0000002B ;*** SPI1S - SPI1 Status Register; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI1S_MODF: equ 4 ; Master Mode Fault Flag
SPI1S_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPI1S_SPRF: equ 7 ; SP1 Read Buffer Full Flag
; bit position masks
mSPI1S_MODF: equ %00010000
mSPI1S_SPTEF: equ %00100000
mSPI1S_SPRF: equ %10000000
;*** SPI1D - SPI1 Data Register; 0x0000002D ***
SPI1D: equ $0000002D ;*** SPI1D - SPI1 Data Register; 0x0000002D ***
;*** SPI2C1 - SPI2 Control Register 1; 0x00000030 ***
SPI2C1: equ $00000030 ;*** SPI2C1 - SPI2 Control Register 1; 0x00000030 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI2C1_LSBFE: equ 0 ; LSB First (shifter direction)
SPI2C1_SSOE: equ 1 ; Slave Select Output Enable
SPI2C1_CPHA: equ 2 ; Clock Phase
SPI2C1_CPOL: equ 3 ; Clock Polarity
SPI2C1_MSTR: equ 4 ; Master/Slave Mode Select
SPI2C1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable
SPI2C1_SPE: equ 6 ; SPI System Enable
SPI2C1_SPIE: equ 7 ; SPI Interrupt Enable
; bit position masks
mSPI2C1_LSBFE: equ %00000001
mSPI2C1_SSOE: equ %00000010
mSPI2C1_CPHA: equ %00000100
mSPI2C1_CPOL: equ %00001000
mSPI2C1_MSTR: equ %00010000
mSPI2C1_SPTIE: equ %00100000
mSPI2C1_SPE: equ %01000000
mSPI2C1_SPIE: equ %10000000
;*** SPI2C2 - SPI2 Control Register 2; 0x00000031 ***
SPI2C2: equ $00000031 ;*** SPI2C2 - SPI2 Control Register 2; 0x00000031 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPI2C2_SPC0: equ 0 ; SPI Pin Control 0
SPI2C2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPI2C2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPI2C2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -