mc9s08lc60.inc
来自「M68HC08及HCS08系列单片机bootloader引导程序源码/示例」· INC 代码 · 共 1,122 行 · 第 1/5 页
INC
1,122 行
;*** ADCCV - Compare Value Register; 0x00000014 ***
ADCCV: equ $00000014 ;*** ADCCV - Compare Value Register; 0x00000014 ***
;*** ADCCVH - Compare Value Register High; 0x00000014 ***
ADCCVH: equ $00000014 ;*** ADCCVH - Compare Value Register High; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCVH_ADCV8: equ 0 ; Compare Function Value 8
ADCCVH_ADCV9: equ 1 ; Compare Function Value 9
ADCCVH_ADCV10: equ 2 ; Compare Function Value 10
ADCCVH_ADCV11: equ 3 ; Compare Function Value 11
; bit position masks
mADCCVH_ADCV8: equ %00000001
mADCCVH_ADCV9: equ %00000010
mADCCVH_ADCV10: equ %00000100
mADCCVH_ADCV11: equ %00001000
;*** ADCCVL - Compare Value Register Low; 0x00000015 ***
ADCCVL: equ $00000015 ;*** ADCCVL - Compare Value Register Low; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCVL_ADCV0: equ 0 ; Compare Function Value 0
ADCCVL_ADCV1: equ 1 ; Compare Function Value 1
ADCCVL_ADCV2: equ 2 ; Compare Function Value 2
ADCCVL_ADCV3: equ 3 ; Compare Function Value 3
ADCCVL_ADCV4: equ 4 ; Compare Function Value 4
ADCCVL_ADCV5: equ 5 ; Compare Function Value 5
ADCCVL_ADCV6: equ 6 ; Compare Function Value 6
ADCCVL_ADCV7: equ 7 ; Compare Function Value 7
; bit position masks
mADCCVL_ADCV0: equ %00000001
mADCCVL_ADCV1: equ %00000010
mADCCVL_ADCV2: equ %00000100
mADCCVL_ADCV3: equ %00001000
mADCCVL_ADCV4: equ %00010000
mADCCVL_ADCV5: equ %00100000
mADCCVL_ADCV6: equ %01000000
mADCCVL_ADCV7: equ %10000000
;*** ADCCFG - Configuration Register; 0x00000016 ***
ADCCFG: equ $00000016 ;*** ADCCFG - Configuration Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCFG_ADICLK0: equ 0 ; Input Clock Select Bit 0
ADCCFG_ADICLK1: equ 1 ; Input Clock Select Bit 1
ADCCFG_MODE0: equ 2 ; Conversion Mode Selection Bit 0
ADCCFG_MODE1: equ 3 ; Conversion Mode Selection Bit 1
ADCCFG_ADLSMP: equ 4 ; Long Sample Time Configuration
ADCCFG_ADIV0: equ 5 ; Clock Divide Select Bit 0
ADCCFG_ADIV1: equ 6 ; Clock Divide Select Bit 1
ADCCFG_ADLPC: equ 7 ; Low Power Configuration
; bit position masks
mADCCFG_ADICLK0: equ %00000001
mADCCFG_ADICLK1: equ %00000010
mADCCFG_MODE0: equ %00000100
mADCCFG_MODE1: equ %00001000
mADCCFG_ADLSMP: equ %00010000
mADCCFG_ADIV0: equ %00100000
mADCCFG_ADIV1: equ %01000000
mADCCFG_ADLPC: equ %10000000
;*** APCTL1 - ADC Pin Control 1 Register; 0x00000017 ***
APCTL1: equ $00000017 ;*** APCTL1 - ADC Pin Control 1 Register; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL1_ADPC0: equ 0 ; ADC Pin Control 0
APCTL1_ADPC1: equ 1 ; ADC Pin Control 1
APCTL1_ADPC2: equ 2 ; ADC Pin Control 2
APCTL1_ADPC3: equ 3 ; ADC Pin Control 3
APCTL1_ADPC4: equ 4 ; ADC Pin Control 4
APCTL1_ADPC5: equ 5 ; ADC Pin Control 5
APCTL1_ADPC6: equ 6 ; ADC Pin Control 6
APCTL1_ADPC7: equ 7 ; ADC Pin Control 7
; bit position masks
mAPCTL1_ADPC0: equ %00000001
mAPCTL1_ADPC1: equ %00000010
mAPCTL1_ADPC2: equ %00000100
mAPCTL1_ADPC3: equ %00001000
mAPCTL1_ADPC4: equ %00010000
mAPCTL1_ADPC5: equ %00100000
mAPCTL1_ADPC6: equ %01000000
mAPCTL1_ADPC7: equ %10000000
;*** IICA - IIC Address Register; 0x00000018 ***
IICA: equ $00000018 ;*** IICA - IIC Address Register; 0x00000018 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICA_ADDR1: equ 1 ; IIC Address Bit 1
IICA_ADDR2: equ 2 ; IIC Address Bit 2
IICA_ADDR3: equ 3 ; IIC Address Bit 3
IICA_ADDR4: equ 4 ; IIC Address Bit 4
IICA_ADDR5: equ 5 ; IIC Address Bit 5
IICA_ADDR6: equ 6 ; IIC Address Bit 6
IICA_ADDR7: equ 7 ; IIC Address Bit 7
; bit position masks
mIICA_ADDR1: equ %00000010
mIICA_ADDR2: equ %00000100
mIICA_ADDR3: equ %00001000
mIICA_ADDR4: equ %00010000
mIICA_ADDR5: equ %00100000
mIICA_ADDR6: equ %01000000
mIICA_ADDR7: equ %10000000
;*** IICF - IIC Frequency Divider Register; 0x00000019 ***
IICF: equ $00000019 ;*** IICF - IIC Frequency Divider Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICF_ICR0: equ 0 ; IIC Clock Rate Bit 0
IICF_ICR1: equ 1 ; IIC Clock Rate Bit 1
IICF_ICR2: equ 2 ; IIC Clock Rate Bit 2
IICF_ICR3: equ 3 ; IIC Clock Rate Bit 3
IICF_ICR4: equ 4 ; IIC Clock Rate Bit 4
IICF_ICR5: equ 5 ; IIC Clock Rate Bit 5
IICF_MULT0: equ 6 ; Multiplier Factor Bit 0
IICF_MULT1: equ 7 ; Multiplier Factor Bit 1
; bit position masks
mIICF_ICR0: equ %00000001
mIICF_ICR1: equ %00000010
mIICF_ICR2: equ %00000100
mIICF_ICR3: equ %00001000
mIICF_ICR4: equ %00010000
mIICF_ICR5: equ %00100000
mIICF_MULT0: equ %01000000
mIICF_MULT1: equ %10000000
;*** IICC - IIC Control Register; 0x0000001A ***
IICC: equ $0000001A ;*** IICC - IIC Control Register; 0x0000001A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICC_RSTA: equ 2 ; Repeat START Bit
IICC_TXAK: equ 3 ; Transmit Acknowledge Enable Bit
IICC_TX: equ 4 ; Transmit Mode Select Bit
IICC_MST: equ 5 ; Master Mode Select Bit
IICC_IICIE: equ 6 ; IIC Interrupt Enable Bit
IICC_IICEN: equ 7 ; IIC Enable Bit
; bit position masks
mIICC_RSTA: equ %00000100
mIICC_TXAK: equ %00001000
mIICC_TX: equ %00010000
mIICC_MST: equ %00100000
mIICC_IICIE: equ %01000000
mIICC_IICEN: equ %10000000
;*** IICS - IIC Status Register; 0x0000001B ***
IICS: equ $0000001B ;*** IICS - IIC Status Register; 0x0000001B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICS_RXAK: equ 0 ; Receive Acknowledge
IICS_IICIF: equ 1 ; IIC Interrupt Flag
IICS_SRW: equ 2 ; Slave Read/Write
IICS_ARBL: equ 4 ; Arbitration Lost
IICS_BUSY: equ 5 ; Bus Busy bit
IICS_IAAS: equ 6 ; Addressed as a Slave Bit
IICS_TCF: equ 7 ; Transfer Complete Flag
; bit position masks
mIICS_RXAK: equ %00000001
mIICS_IICIF: equ %00000010
mIICS_SRW: equ %00000100
mIICS_ARBL: equ %00010000
mIICS_BUSY: equ %00100000
mIICS_IAAS: equ %01000000
mIICS_TCF: equ %10000000
;*** IICD - IIC Data I/O Register; 0x0000001C ***
IICD: equ $0000001C ;*** IICD - IIC Data I/O Register; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICD_DATA0: equ 0 ; IIC Data Bit 0
IICD_DATA1: equ 1 ; IIC Data Bit 1
IICD_DATA2: equ 2 ; IIC Data Bit 2
IICD_DATA3: equ 3 ; IIC Data Bit 3
IICD_DATA4: equ 4 ; IIC Data Bit 4
IICD_DATA5: equ 5 ; IIC Data Bit 5
IICD_DATA6: equ 6 ; IIC Data Bit 6
IICD_DATA7: equ 7 ; IIC Data Bit 7
; bit position masks
mIICD_DATA0: equ %00000001
mIICD_DATA1: equ %00000010
mIICD_DATA2: equ %00000100
mIICD_DATA3: equ %00001000
mIICD_DATA4: equ %00010000
mIICD_DATA5: equ %00100000
mIICD_DATA6: equ %01000000
mIICD_DATA7: equ %10000000
;*** SCIBD - SCI Baud Rate Register; 0x00000020 ***
SCIBD: equ $00000020 ;*** SCIBD - SCI Baud Rate Register; 0x00000020 ***
;*** SCIBDH - SCI Baud Rate Register High; 0x00000020 ***
SCIBDH: equ $00000020 ;*** SCIBDH - SCI Baud Rate Register High; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIBDH_SBR8: equ 0 ; Baud Rate Modulo Divisor Bit 8
SCIBDH_SBR9: equ 1 ; Baud Rate Modulo Divisor Bit 9
SCIBDH_SBR10: equ 2 ; Baud Rate Modulo Divisor Bit 10
SCIBDH_SBR11: equ 3 ; Baud Rate Modulo Divisor Bit 11
SCIBDH_SBR12: equ 4 ; Baud Rate Modulo Divisor Bit 12
; bit position masks
mSCIBDH_SBR8: equ %00000001
mSCIBDH_SBR9: equ %00000010
mSCIBDH_SBR10: equ %00000100
mSCIBDH_SBR11: equ %00001000
mSCIBDH_SBR12: equ %00010000
;*** SCIBDL - SCI Baud Rate Register Low; 0x00000021 ***
SCIBDL: equ $00000021 ;*** SCIBDL - SCI Baud Rate Register Low; 0x00000021 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIBDL_SBR0: equ 0 ; Baud Rate Modulo Divisor Bit 0
SCIBDL_SBR1: equ 1 ; Baud Rate Modulo Divisor Bit 1
SCIBDL_SBR2: equ 2 ; Baud Rate Modulo Divisor Bit 2
SCIBDL_SBR3: equ 3 ; Baud Rate Modulo Divisor Bit 3
SCIBDL_SBR4: equ 4 ; Baud Rate Modulo Divisor Bit 4
SCIBDL_SBR5: equ 5 ; Baud Rate Modulo Divisor Bit 5
SCIBDL_SBR6: equ 6 ; Baud Rate Modulo Divisor Bit 6
SCIBDL_SBR7: equ 7 ; Baud Rate Modulo Divisor Bit 7
; bit position masks
mSCIBDL_SBR0: equ %00000001
mSCIBDL_SBR1: equ %00000010
mSCIBDL_SBR2: equ %00000100
mSCIBDL_SBR3: equ %00001000
mSCIBDL_SBR4: equ %00010000
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