📄 slfprg-s08qg-softsci.asm
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;*********************************************************************
; HEADER_START
;
; $File Name: slfprg-s08qg-softsci.asm$
; Project: Developper's HC08 Bootloader Slave
; Description: S08QG main bootloader file, software SCI
; Platform: HCS08
; $Version: 8.0.7.0$
; $Date: Mar-14-2008$
; $Last Modified By: r30323$
; Company: Freescale Semiconductor
; Security: General Business
;
; ===================================================================
; Copyright (c): Freescale Semiconductor, 2006, All rights reserved.
;
; ===================================================================
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END
; only labels PLATFORM and IRQOPTION defined externally:
;
; PLATFORM = 1,2,3... once you create your own platform (combination or RXD and TXD
; pins, together with polarity, memory size, etc.), add a new target with new platform
; number and add a new section woth defines for this platform.
;
; IRQOPTION *NOT* defined >> regular version
; IRQOPTION defined >> regular version using IRQ option (bootloading won't start if IRQ high)
;
; The bootloader starts communicating at 9600Bd but with calibration feature,
; the communication speeds up to 57600Bd were briefly tested (the embedded side
; will automatically calibrate to such speed without any code change).
include "mc9s08qg8.inc"
;##########################################################################
;##########################################################################
IF PLATFORM = 1 ; TRA0
RCS_ENA EQU 1 ; READ COMMAND SUPPORTED?
SIZE EQU 8 ; specify YOUR memory size
TXDPORT EQU PTAD ; <<< TxD pin port
TXDPIN EQU PTAD_PTAD0 ; <<< TxD pin number
SCITXINV EQU 0 ; 0 with level shifters, 1 without
SCIRXINV EQU SCITXINV ; 0 with level shifters, 1 without
RXDPORT EQU PTAD ; <<< RxD pin port
RXDPIN EQU PTAD_PTAD0 ; <<< RxD pin number
RXDPUEN EQU 1 ; use pull-up feature
RXDPUE EQU PTAPE ; define pull-up enable port, if used
ENDIF
;**************************************************************************
IF PLATFORM = 2 ; TB1RB0
RCS_ENA EQU 1 ; READ COMMAND SUPPORTED?
SIZE EQU 8 ; specify YOUR memory size
TXDPORT EQU PTBD ; <<< TxD pin port
TXDPIN EQU PTBD_PTBD1 ; <<< TxD pin number
SCITXINV EQU 0 ; 0 with level shifters, 1 without
SCIRXINV EQU SCITXINV ; 0 with level shifters, 1 without
RXDPORT EQU PTBD ; <<< RxD pin port
RXDPIN EQU PTBD_PTBD0 ; <<< RxD pin number
RXDPUEN EQU 1 ; use pull-up feature
RXDPUE EQU PTBPE ; define pull-up enable port, if used
ENDIF
;**************************************************************************
IF PLATFORM = 3 ; TRiB6
RCS_ENA EQU 1 ; READ COMMAND SUPPORTED?
SIZE EQU 8 ; specify YOUR memory size
TXDPORT EQU PTBD ; <<< TxD pin port
TXDPIN EQU PTBD_PTBD6 ; <<< TxD pin number
SCITXINV EQU 1 ; 0 with level shifters, 1 without
SCIRXINV EQU SCITXINV ; 0 with level shifters, 1 without
RXDPORT EQU PTBD ; <<< RxD pin port
RXDPIN EQU PTBD_PTBD6 ; <<< RxD pin number
RXDPUEN EQU 0 ; use pull-up feature
RXDPUE EQU PTBPE ; define pull-up enable port, if used
ENDIF
;##########################################################################
;##########################################################################
; the code below should not be modified (too much)
;**************************************************************************
IF (RXDPORT = TXDPORT) & (RXDPIN = TXDPIN)
SINGLEWIRE EQU 1 ; do use single-wire feature
ELSE
SINGLEWIRE EQU 0 ; do NOT use single-wire feature
ENDIF
;**************************************************************************
TXDDDR EQU TXDPORT+1
RXDDDR EQU RXDPORT+1
BUSCLOCK EQU 8000000 ; QG's BUS clock
SCISPEED EQU 9600
SCITXTICK EQU (BUSCLOCK/SCISPEED)
;*******************************************************************************************
IF RCS_ENA = 1
RCS EQU $80 ; READ COMMAND SUPPORTED
ELSE
RCS EQU 0 ; READ COMMAND unSUPPORTED
ENDIF
VER_NUM EQU 2 ; FC protocol version number
IDENTS MACRO
DC.B 'QG'
IF SIZE = 8
DC.B '8' ; 8kb string
ENDIF
IF SIZE = 4
DC.B '4' ; 4kb string
ENDIF
DC.B '-softSCI'
IFDEF IRQOPTION
DC.B '-irq' ; IRQ option used
ENDIF
DC.B 0
ENDM
ERBLK_LEN EQU 512
WRBLK_LEN EQU 64
IF SIZE = 8
FLS_BEG EQU $E000 ; FLASH #0 block start
FLS_END EQU $FDC0 ; FLASH #0 block end
ENDIF
IF SIZE = 4
FLS_BEG EQU $F000 ; FLASH #0 block start
FLS_END EQU $FDC0 ; FLASH #0 block end
ENDIF
REL_VECT EQU $FDC0 ; newly relocated int. vectors
INT_VECT EQU $FFC0 ; start of table of original vectros!
; command codes
mBlank: equ $05 ;Blank Check command
mByteProg: equ $20 ;Byte Program command
mBurstProg: equ $25 ;Burst Program command
mPageErase: equ $40 ;Page Erase command
mMassErase: equ $41 ;Mass Erase command
F_ICSTRM equ $FFAF
F_ICSFTRM equ $FFAE
XDEF main
;*******************************************************************************************
WR_DATA EQU 'W'
RD_DATA EQU 'R'
ENDPRG EQU 'Q'
ERASE EQU 'E'
ACK EQU $FC
IDENT EQU 'I'
T100MS EQU 255
ILOP MACRO
DC.B $8d ; this is illegal operation code
ENDM
SKIP1 MACRO
DC.B $21 ; BRANCH NEVER (saves memory)
ENDM
SKIP2 MACRO
DC.B $65 ; CPHX (saves memory)
ENDM
BRRXDLO MACRO
IF SCIRXINV = 1
BRSET RXDPIN,RXDPORT,\1 ; branch if RXD low
ELSE
BRCLR RXDPIN,RXDPORT,\1 ; branch if RXD low
ENDIF
ENDM
BRRXDHI MACRO
IF SCIRXINV = 1
BRCLR RXDPIN,RXDPORT,\1 ; branch if RXD hi
ELSE
BRSET RXDPIN,RXDPORT,\1 ; branch if RXD hi
ENDIF
ENDM
TXDCLR MACRO
IF SCITXINV = 1
BSET TXDPIN,TXDPORT ; clr bit
ELSE
BCLR TXDPIN,TXDPORT ; clr bit
ENDIF
ENDM
TXDSET MACRO
IF SCITXINV = 1
BCLR TXDPIN,TXDPORT ; set bit
ELSE
BSET TXDPIN,TXDPORT ; set bit
ENDIF
ENDM
;*******************************************************************************************
MY_ZEROPAGE: SECTION SHORT
ONEBIT: DS.W 1 ; length of 1 bit (in BUS clock cycles)
BITS: DS.B 1 ; bit counter in RX/TX softSCI routines
ADRS: DS.W 1 ; target flash address
ADRR: DS.W 1 ; pointer to source data in RAM
LEN: DS.B 1 ; lenght counter
STAT: DS.B 1 ; temporary length counter
STACK: DS.W 1 ; temporary storage for SP
DEFAULT_RAM: SECTION
DATA: DS.B WRBLK_LEN ; buffer for Write data
;*******************************************************************************************
DEFAULT_ROM: SECTION
ID_STRING:
DC.B 1 ; number of Flash blocks
DC.W FLS_BEG ; START ADDRESS OF FLASH
DC.W FLS_END ; END ADDRESS OF FLASH
DC.W REL_VECT ; POINTER TO APPLICATION VECTOR TABLE
DC.W INT_VECT ; POINTER TO BEGINING OF FLASH INT. VECTORS
DC.W ERBLK_LEN ; ERASE BLCK LENGTH OF FLASH ALG.
DC.W WRBLK_LEN ; WRITE BLCK LENGTH OF FLASH ALG.
IDENTS
ID_STRING_END:
XDEF MY_NVPROT
XDEF MY_NVOPT
;*******************************************************************************************
NVPROT_ROM: SECTION
MY_NVPROT DC.B %11111100 ; flash protected (from 0xFE00)
NVOPT_ROM: SECTION
MY_NVOPT DC.B %10000010 ; backdoor enable, redirection enable, (un)secured flash [last 10]
DEFAULT_ROM: SECTION
;*******************************************************************************************
main:
IFDEF IRQOPTION
BIH PVEC0 ; if IRQ high, jump directly to real app.
ENDIF
LDA SRS ; fetch RESET status reg.
TSTA ; check if zero (this happens if RESET pulse is too short)
BEQ slfprg ; if so, jump to self programming
AND #%10000000 ; mask only POR RESET source
BNE slfprg ; any of these sources, go to self programming
PVEC0:
LDHX #(REL_VECT|$00FF)&$FFFE ; there should be relocated reset vector of the new app.
LDA ,X
PSHA
AND 1,X
LDX 1,X
PULH
INCA
BEQ slfprg ; don't jump if empty vector!
JMP ,X ; jump to relocated application!
slfprg:
LDA F_ICSTRM
STA ICSTRM
LDA F_ICSFTRM
ORA ICSSC
STA ICSSC
LDA #%00000010
STA SOPT1 ; COP disable, BDM enable (for now)
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