📄 mc9s08qg8.inc
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mIICC_TX: equ %00010000
mIICC_MST: equ %00100000
mIICC_IICIE: equ %01000000
mIICC_IICEN: equ %10000000
;*** IICS - IIC Status Register; 0x00000033 ***
IICS: equ $00000033 ;*** IICS - IIC Status Register; 0x00000033 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICS_RXAK: equ 0 ; Receive Acknowledge
IICS_IICIF: equ 1 ; IIC Interrupt Flag
IICS_SRW: equ 2 ; Slave Read/Write
IICS_ARBL: equ 4 ; Arbitration Lost
IICS_BUSY: equ 5 ; Bus Busy bit
IICS_IAAS: equ 6 ; Addressed as a Slave Bit
IICS_TCF: equ 7 ; Transfer Complete Flag
; bit position masks
mIICS_RXAK: equ %00000001
mIICS_IICIF: equ %00000010
mIICS_SRW: equ %00000100
mIICS_ARBL: equ %00010000
mIICS_BUSY: equ %00100000
mIICS_IAAS: equ %01000000
mIICS_TCF: equ %10000000
;*** IICD - IIC Data I/O Register; 0x00000034 ***
IICD: equ $00000034 ;*** IICD - IIC Data I/O Register; 0x00000034 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICD_DATA0: equ 0 ; IIC Data Bit 0
IICD_DATA1: equ 1 ; IIC Data Bit 1
IICD_DATA2: equ 2 ; IIC Data Bit 2
IICD_DATA3: equ 3 ; IIC Data Bit 3
IICD_DATA4: equ 4 ; IIC Data Bit 4
IICD_DATA5: equ 5 ; IIC Data Bit 5
IICD_DATA6: equ 6 ; IIC Data Bit 6
IICD_DATA7: equ 7 ; IIC Data Bit 7
; bit position masks
mIICD_DATA0: equ %00000001
mIICD_DATA1: equ %00000010
mIICD_DATA2: equ %00000100
mIICD_DATA3: equ %00001000
mIICD_DATA4: equ %00010000
mIICD_DATA5: equ %00100000
mIICD_DATA6: equ %01000000
mIICD_DATA7: equ %10000000
;*** ICSC1 - ICS Control Register 1; 0x00000038 ***
ICSC1: equ $00000038 ;*** ICSC1 - ICS Control Register 1; 0x00000038 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC1_IREFSTEN: equ 0 ; Internal Reference Stop Enable
ICSC1_IRCLKEN: equ 1 ; Internal Reference Clock Enable
ICSC1_IREFS: equ 2 ; Internal Reference Select
ICSC1_RDIV0: equ 3 ; Reference Divider, bit 0
ICSC1_RDIV1: equ 4 ; Reference Divider, bit 1
ICSC1_RDIV2: equ 5 ; Reference Divider, bit 2
ICSC1_CLKS0: equ 6 ; Clock Source Select, bit 0
ICSC1_CLKS1: equ 7 ; Clock Source Select, bit 1
; bit position masks
mICSC1_IREFSTEN: equ %00000001
mICSC1_IRCLKEN: equ %00000010
mICSC1_IREFS: equ %00000100
mICSC1_RDIV0: equ %00001000
mICSC1_RDIV1: equ %00010000
mICSC1_RDIV2: equ %00100000
mICSC1_CLKS0: equ %01000000
mICSC1_CLKS1: equ %10000000
;*** ICSC2 - ICS Control Register 2; 0x00000039 ***
ICSC2: equ $00000039 ;*** ICSC2 - ICS Control Register 2; 0x00000039 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC2_EREFSTEN: equ 0 ; External Reference Stop Enable
ICSC2_ERCLKEN: equ 1 ; External Reference Enable
ICSC2_EREFS: equ 2 ; External Reference Select
ICSC2_LP: equ 3 ; Low Power Select
ICSC2_HGO: equ 4 ; High Gain Oscillator Select
ICSC2_RANGE: equ 5 ; Frequency Range Select
ICSC2_BDIV0: equ 6 ; Bus Frequency Divider, bit 0
ICSC2_BDIV1: equ 7 ; Bus Frequency Divider, bit 1
; bit position masks
mICSC2_EREFSTEN: equ %00000001
mICSC2_ERCLKEN: equ %00000010
mICSC2_EREFS: equ %00000100
mICSC2_LP: equ %00001000
mICSC2_HGO: equ %00010000
mICSC2_RANGE: equ %00100000
mICSC2_BDIV0: equ %01000000
mICSC2_BDIV1: equ %10000000
;*** ICSTRM - ICS Trim Register; 0x0000003A ***
ICSTRM: equ $0000003A ;*** ICSTRM - ICS Trim Register; 0x0000003A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSTRM_TRIM0: equ 0 ; ICS Trim Setting, bit 0
ICSTRM_TRIM1: equ 1 ; ICS Trim Setting, bit 1
ICSTRM_TRIM2: equ 2 ; ICS Trim Setting, bit 2
ICSTRM_TRIM3: equ 3 ; ICS Trim Setting, bit 3
ICSTRM_TRIM4: equ 4 ; ICS Trim Setting, bit 4
ICSTRM_TRIM5: equ 5 ; ICS Trim Setting, bit 5
ICSTRM_TRIM6: equ 6 ; ICS Trim Setting, bit 6
ICSTRM_TRIM7: equ 7 ; ICS Trim Setting, bit 7
; bit position masks
mICSTRM_TRIM0: equ %00000001
mICSTRM_TRIM1: equ %00000010
mICSTRM_TRIM2: equ %00000100
mICSTRM_TRIM3: equ %00001000
mICSTRM_TRIM4: equ %00010000
mICSTRM_TRIM5: equ %00100000
mICSTRM_TRIM6: equ %01000000
mICSTRM_TRIM7: equ %10000000
;*** ICSSC - ICS Status and Control; 0x0000003B ***
ICSSC: equ $0000003B ;*** ICSSC - ICS Status and Control; 0x0000003B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSSC_FTRIM: equ 0 ; ICS Fine Trim
ICSSC_OSCINIT: equ 1 ; OSC Initialization
ICSSC_CLKST0: equ 2 ; Clock Mode Status, bit 0
ICSSC_CLKST1: equ 3 ; Clock Mode Status, bit 1
; bit position masks
mICSSC_FTRIM: equ %00000001
mICSSC_OSCINIT: equ %00000010
mICSSC_CLKST0: equ %00000100
mICSSC_CLKST1: equ %00001000
;*** MTIMSC - MTIM Status and Control Register; 0x0000003C ***
MTIMSC: equ $0000003C ;*** MTIMSC - MTIM Status and Control Register; 0x0000003C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MTIMSC_TSTP: equ 4 ; MTIM Counter Stop
MTIMSC_TRST: equ 5 ; MTIM Counter Reset
MTIMSC_TOIE: equ 6 ; MTIM Overflow Interrupt Enable
MTIMSC_TOF: equ 7 ; MTIM Overflow Flag
; bit position masks
mMTIMSC_TSTP: equ %00010000
mMTIMSC_TRST: equ %00100000
mMTIMSC_TOIE: equ %01000000
mMTIMSC_TOF: equ %10000000
;*** MTIMCLK - MTIM Clock Configuration Register; 0x0000003D ***
MTIMCLK: equ $0000003D ;*** MTIMCLK - MTIM Clock Configuration Register; 0x0000003D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MTIMCLK_PS0: equ 0 ; Clock Source Prescaler, bit 0
MTIMCLK_PS1: equ 1 ; Clock Source Prescaler, bit 1
MTIMCLK_PS2: equ 2 ; Clock Source Prescaler, bit 2
MTIMCLK_PS3: equ 3 ; Clock Source Prescaler, bit 3
MTIMCLK_CLKS0: equ 4 ; Clock Source Select, bit 0
MTIMCLK_CLKS1: equ 5 ; Clock Source Select, bit 1
; bit position masks
mMTIMCLK_PS0: equ %00000001
mMTIMCLK_PS1: equ %00000010
mMTIMCLK_PS2: equ %00000100
mMTIMCLK_PS3: equ %00001000
mMTIMCLK_CLKS0: equ %00010000
mMTIMCLK_CLKS1: equ %00100000
;*** MTIMCNT - MTIM Counter Register; 0x0000003E ***
MTIMCNT: equ $0000003E ;*** MTIMCNT - MTIM Counter Register; 0x0000003E ***
;*** MTIMMOD - MTIM Modulo Register; 0x0000003F ***
MTIMMOD: equ $0000003F ;*** MTIMMOD - MTIM Modulo Register; 0x0000003F ***
;*** TPMSC - TPM Timer Status and Control Register; 0x00000040 ***
TPMSC: equ $00000040 ;*** TPMSC - TPM Timer Status and Control Register; 0x00000040 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPMSC_PS0: equ 0 ; Prescale Divisor Select Bit 0
TPMSC_PS1: equ 1 ; Prescale Divisor Select Bit 1
TPMSC_PS2: equ 2 ; Prescale Divisor Select Bit 2
TPMSC_CLKSA: equ 3 ; Clock Source Select A
TPMSC_CLKSB: equ 4 ; Clock Source Select B
TPMSC_CPWMS: equ 5 ; Center-Aligned PWM Select
TPMSC_TOIE: equ 6 ; Timer Overflow Interrupt Enable
TPMSC_TOF: equ 7 ; Timer Overflow Flag
; bit position masks
mTPMSC_PS0: equ %00000001
mTPMSC_PS1: equ %00000010
mTPMSC_PS2: equ %00000100
mTPMSC_CLKSA: equ %00001000
mTPMSC_CLKSB: equ %00010000
mTPMSC_CPWMS: equ %00100000
mTPMSC_TOIE: equ %01000000
mTPMSC_TOF: equ %10000000
;*** TPMCNT - TPM Counter Register; 0x00000041 ***
TPMCNT: equ $00000041 ;*** TPMCNT - TPM Counter Register; 0x00000041 ***
;*** TPMCNTH - TPM Counter Register High; 0x00000041 ***
TPMCNTH: equ $00000041 ;*** TPMCNTH - TPM Counter Register High; 0x00000041 ***
;*** TPMCNTL - TPM Counter Register Low; 0x00000042 ***
TPMCNTL: equ $00000042 ;*** TPMCNTL - TPM Counter Register Low; 0x00000042 ***
;*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000043 ***
TPMMOD: equ $00000043 ;*** TPMMOD - TPM Timer Counter Modulo Register; 0x00000043 ***
;*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000043 ***
TPMMODH: equ $00000043 ;*** TPMMODH - TPM Timer Counter Modulo Register High; 0x00000043 ***
;*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000044 ***
TPMMODL: equ $00000044 ;*** TPMMODL - TPM Timer Counter Modulo Register Low; 0x00000044 ***
;*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000045 ***
TPMC0SC: equ $00000045 ;*** TPMC0SC - TPM Timer Channel 0 Status and Control Register; 0x00000045 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPMC0SC_ELS0A: equ 2 ; Edge/Level Select Bit A
TPMC0SC_ELS0B: equ 3 ; Edge/Level Select Bit B
TPMC0SC_MS0A: equ 4 ; Mode Select A for TPM Channel 0
TPMC0SC_MS0B: equ 5 ; Mode Select B for TPM Channel 0
TPMC0SC_CH0IE: equ 6 ; Channel 0 Interrupt Enable
TPMC0SC_CH0F: equ 7 ; Channel 0 Flag
; bit position masks
mTPMC0SC_ELS0A: equ %00000100
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