📄 mc9s08qg8.inc
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mSCIC1_LOOPS: equ %10000000
;*** SCIC2 - SCI Control Register 2; 0x00000023 ***
SCIC2: equ $00000023 ;*** SCIC2 - SCI Control Register 2; 0x00000023 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC2_SBK: equ 0 ; Send Break
SCIC2_RWU: equ 1 ; Receiver Wakeup Control
SCIC2_RE: equ 2 ; Receiver Enable
SCIC2_TE: equ 3 ; Transmitter Enable
SCIC2_ILIE: equ 4 ; Idle Line Interrupt Enable (for IDLE)
SCIC2_RIE: equ 5 ; Receiver Interrupt Enable (for RDRF)
SCIC2_TCIE: equ 6 ; Transmission Complete Interrupt Enable (for TC)
SCIC2_TIE: equ 7 ; Transmit Interrupt Enable (for TDRE)
; bit position masks
mSCIC2_SBK: equ %00000001
mSCIC2_RWU: equ %00000010
mSCIC2_RE: equ %00000100
mSCIC2_TE: equ %00001000
mSCIC2_ILIE: equ %00010000
mSCIC2_RIE: equ %00100000
mSCIC2_TCIE: equ %01000000
mSCIC2_TIE: equ %10000000
;*** SCIS1 - SCI Status Register 1; 0x00000024 ***
SCIS1: equ $00000024 ;*** SCIS1 - SCI Status Register 1; 0x00000024 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIS1_PF: equ 0 ; Parity Error Flag
SCIS1_FE: equ 1 ; Framing Error Flag
SCIS1_NF: equ 2 ; Noise Flag
SCIS1_OR: equ 3 ; Receiver Overrun Flag
SCIS1_IDLE: equ 4 ; Idle Line Flag
SCIS1_RDRF: equ 5 ; Receive Data Register Full Flag
SCIS1_TC: equ 6 ; Transmission Complete Flag
SCIS1_TDRE: equ 7 ; Transmit Data Register Empty Flag
; bit position masks
mSCIS1_PF: equ %00000001
mSCIS1_FE: equ %00000010
mSCIS1_NF: equ %00000100
mSCIS1_OR: equ %00001000
mSCIS1_IDLE: equ %00010000
mSCIS1_RDRF: equ %00100000
mSCIS1_TC: equ %01000000
mSCIS1_TDRE: equ %10000000
;*** SCIS2 - SCI Status Register 2; 0x00000025 ***
SCIS2: equ $00000025 ;*** SCIS2 - SCI Status Register 2; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIS2_RAF: equ 0 ; Receiver Active Flag
SCIS2_BRK13: equ 2 ; Break Character Length
; bit position masks
mSCIS2_RAF: equ %00000001
mSCIS2_BRK13: equ %00000100
;*** SCIC3 - SCI Control Register 3; 0x00000026 ***
SCIC3: equ $00000026 ;*** SCIC3 - SCI Control Register 3; 0x00000026 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCIC3_PEIE: equ 0 ; Parity Error Interrupt Enable
SCIC3_FEIE: equ 1 ; Framing Error Interrupt Enable
SCIC3_NEIE: equ 2 ; Noise Error Interrupt Enable
SCIC3_ORIE: equ 3 ; Overrun Interrupt Enable
SCIC3_TXINV: equ 4 ; Transmit Data Inversion
SCIC3_TXDIR: equ 5 ; TxD Pin Direction in Single-Wire Mode
SCIC3_T8: equ 6 ; Ninth Data Bit for Transmitter
SCIC3_R8: equ 7 ; Ninth Data Bit for Receiver
; bit position masks
mSCIC3_PEIE: equ %00000001
mSCIC3_FEIE: equ %00000010
mSCIC3_NEIE: equ %00000100
mSCIC3_ORIE: equ %00001000
mSCIC3_TXINV: equ %00010000
mSCIC3_TXDIR: equ %00100000
mSCIC3_T8: equ %01000000
mSCIC3_R8: equ %10000000
;*** SCID - SCI Data Register; 0x00000027 ***
SCID: equ $00000027 ;*** SCID - SCI Data Register; 0x00000027 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SCID_R0_T0: equ 0 ; Receive/Transmit Data Bit 0
SCID_R1_T1: equ 1 ; Receive/Transmit Data Bit 1
SCID_R2_T2: equ 2 ; Receive/Transmit Data Bit 2
SCID_R3_T3: equ 3 ; Receive/Transmit Data Bit 3
SCID_R4_T4: equ 4 ; Receive/Transmit Data Bit 4
SCID_R5_T5: equ 5 ; Receive/Transmit Data Bit 5
SCID_R6_T6: equ 6 ; Receive/Transmit Data Bit 6
SCID_R7_T7: equ 7 ; Receive/Transmit Data Bit 7
; bit position masks
mSCID_R0_T0: equ %00000001
mSCID_R1_T1: equ %00000010
mSCID_R2_T2: equ %00000100
mSCID_R3_T3: equ %00001000
mSCID_R4_T4: equ %00010000
mSCID_R5_T5: equ %00100000
mSCID_R6_T6: equ %01000000
mSCID_R7_T7: equ %10000000
;*** SPIC1 - SPI Control Register 1; 0x00000028 ***
SPIC1: equ $00000028 ;*** SPIC1 - SPI Control Register 1; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIC1_LSBFE: equ 0 ; LSB First (shifter direction)
SPIC1_SSOE: equ 1 ; Slave Select Output Enable
SPIC1_CPHA: equ 2 ; Clock Phase
SPIC1_CPOL: equ 3 ; Clock Polarity
SPIC1_MSTR: equ 4 ; Master/Slave Mode Select
SPIC1_SPTIE: equ 5 ; SPI Transmit Interrupt Enable
SPIC1_SPE: equ 6 ; SPI System Enable
SPIC1_SPIE: equ 7 ; SPI Interrupt Enable
; bit position masks
mSPIC1_LSBFE: equ %00000001
mSPIC1_SSOE: equ %00000010
mSPIC1_CPHA: equ %00000100
mSPIC1_CPOL: equ %00001000
mSPIC1_MSTR: equ %00010000
mSPIC1_SPTIE: equ %00100000
mSPIC1_SPE: equ %01000000
mSPIC1_SPIE: equ %10000000
;*** SPIC2 - SPI Control Register 2; 0x00000029 ***
SPIC2: equ $00000029 ;*** SPIC2 - SPI Control Register 2; 0x00000029 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIC2_SPC0: equ 0 ; SPI Pin Control 0
SPIC2_SPISWAI: equ 1 ; SPI Stop in Wait Mode
SPIC2_BIDIROE: equ 3 ; Bidirectional Mode Output Enable
SPIC2_MODFEN: equ 4 ; Master Mode-Fault Function Enable
; bit position masks
mSPIC2_SPC0: equ %00000001
mSPIC2_SPISWAI: equ %00000010
mSPIC2_BIDIROE: equ %00001000
mSPIC2_MODFEN: equ %00010000
;*** SPIBR - SPI Baud Rate Register; 0x0000002A ***
SPIBR: equ $0000002A ;*** SPIBR - SPI Baud Rate Register; 0x0000002A ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIBR_SPR0: equ 0 ; SPI Baud Rate Divisor Bit 0
SPIBR_SPR1: equ 1 ; SPI Baud Rate Divisor Bit 1
SPIBR_SPR2: equ 2 ; SPI Baud Rate Divisor Bit 2
SPIBR_SPPR0: equ 4 ; SPI Baud Rate Prescale Divisor Bit 0
SPIBR_SPPR1: equ 5 ; SPI Baud Rate Prescale Divisor Bit 1
SPIBR_SPPR2: equ 6 ; SPI Baud Rate Prescale Divisor Bit 2
; bit position masks
mSPIBR_SPR0: equ %00000001
mSPIBR_SPR1: equ %00000010
mSPIBR_SPR2: equ %00000100
mSPIBR_SPPR0: equ %00010000
mSPIBR_SPPR1: equ %00100000
mSPIBR_SPPR2: equ %01000000
;*** SPIS - SPI Status Register; 0x0000002B ***
SPIS: equ $0000002B ;*** SPIS - SPI Status Register; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SPIS_MODF: equ 4 ; Master Mode Fault Flag
SPIS_SPTEF: equ 5 ; SPI Transmit Buffer Empty Flag
SPIS_SPRF: equ 7 ; SPI Read Buffer Full Flag
; bit position masks
mSPIS_MODF: equ %00010000
mSPIS_SPTEF: equ %00100000
mSPIS_SPRF: equ %10000000
;*** SPID - SPI Data Register; 0x0000002D ***
SPID: equ $0000002D ;*** SPID - SPI Data Register; 0x0000002D ***
;*** IICA - IIC Address Register; 0x00000030 ***
IICA: equ $00000030 ;*** IICA - IIC Address Register; 0x00000030 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICA_ADDR0: equ 1 ; IIC Address Bit 0
IICA_ADDR1: equ 2 ; IIC Address Bit 1
IICA_ADDR2: equ 3 ; IIC Address Bit 2
IICA_ADDR3: equ 4 ; IIC Address Bit 3
IICA_ADDR4: equ 5 ; IIC Address Bit 4
IICA_ADDR5: equ 6 ; IIC Address Bit 5
IICA_ADDR6: equ 7 ; IIC Address Bit 6
; bit position masks
mIICA_ADDR0: equ %00000010
mIICA_ADDR1: equ %00000100
mIICA_ADDR2: equ %00001000
mIICA_ADDR3: equ %00010000
mIICA_ADDR4: equ %00100000
mIICA_ADDR5: equ %01000000
mIICA_ADDR6: equ %10000000
;*** IICF - IIC Frequency Divider Register; 0x00000031 ***
IICF: equ $00000031 ;*** IICF - IIC Frequency Divider Register; 0x00000031 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICF_ICR0: equ 0 ; IIC Clock Rate Bit 0
IICF_ICR1: equ 1 ; IIC Clock Rate Bit 1
IICF_ICR2: equ 2 ; IIC Clock Rate Bit 2
IICF_ICR3: equ 3 ; IIC Clock Rate Bit 3
IICF_ICR4: equ 4 ; IIC Clock Rate Bit 4
IICF_ICR5: equ 5 ; IIC Clock Rate Bit 5
IICF_MULT0: equ 6 ; Multiplier Factor Bit 0
IICF_MULT1: equ 7 ; Multiplier Factor Bit 1
; bit position masks
mIICF_ICR0: equ %00000001
mIICF_ICR1: equ %00000010
mIICF_ICR2: equ %00000100
mIICF_ICR3: equ %00001000
mIICF_ICR4: equ %00010000
mIICF_ICR5: equ %00100000
mIICF_MULT0: equ %01000000
mIICF_MULT1: equ %10000000
;*** IICC - IIC Control Register; 0x00000032 ***
IICC: equ $00000032 ;*** IICC - IIC Control Register; 0x00000032 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IICC_RSTA: equ 2 ; Repeat START Bit
IICC_TXAK: equ 3 ; Transmit Acknowledge Enable Bit
IICC_TX: equ 4 ; Transmit Mode Select Bit
IICC_MST: equ 5 ; Master Mode Select Bit
IICC_IICIE: equ 6 ; IIC Interrupt Enable Bit
IICC_IICEN: equ 7 ; IIC Enable Bit
; bit position masks
mIICC_RSTA: equ %00000100
mIICC_TXAK: equ %00001000
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