slfprg-s08dz128.asm

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

;*********************************************************************
; HEADER_START
;
;  	   $File Name: slfprg-s08dz128.asm$
;      Project:        Developper's HC08 Bootloader Slave
;      Description:    S08DZ128 main bootloader file
;      Platform:       HCS08
;      $Version: 9.0.3.0$
;      $Date: Jun-13-2008$ 
;      $Last Modified By: r30323$
;      Company:        Freescale Semiconductor
;      Security:       General Business
;
; =================================================================== 
; Copyright (c):      Freescale Semiconductor, 2008, All rights reserved.
;
; =================================================================== 
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END

; labels SCI, SIZE and IRQOPTION defined externally:
; SIZE = 96, 128 depending whether what memory size of DZ/DV family is required
; if EEPROM is defined -> DZ family used (EEPROM support)
; if EEPROM is *NOT* defined, it defaults to DV family (no EEPROM support)
; 
; IRQOPTION *NOT* defined >> regular version (bootloader starts always after POR)
; IRQOPTION defined >> using IRQ option (bootloading won't start if IRQ high)
;
; label SCI = 1, 2 selects what SCI channel is used
; label HISPEED => if defined, 38400Bd is used instead of 9600Bd


;!!!;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;!!!
;!!!   This S08DZ128 bootloader requires hc08sprg.exe of version 9.0.41.0 or higher
;!!!
;!!!;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;


	include "mc9s08dz128.inc"

	IFNDEF SCI
SCI		EQU		1
	ENDIF	


PF          equ    0
FE          equ    1
NF          equ    2
OR          equ    3
IDLE        equ    4
RDRF        equ    5
TC          equ    6
TDRE        equ    7

	IF SCI = 1
SCIBDH	equ SCI1BDH
SCIBDL	equ SCI1BDL
SCC1  	equ SCI1C1
SCC2  	equ SCI1C2
SCC3  	equ SCI1C3
SCS1  	equ SCI1S1
SCS2  	equ SCI1S2
SCDR  	equ SCI1D

	ENDIF

	IF SCI = 2
SCIBDH	equ SCI2BDH
SCIBDL	equ SCI2BDL
SCC1  	equ SCI2C1
SCC2  	equ SCI2C2
SCC3  	equ SCI2C3
SCS1  	equ SCI2S1
SCS2  	equ SCI2S2
SCDR  	equ SCI2D

	ENDIF


RCS_ENA    	EQU     1     	; READ COMMAND SUPPORTED?

  IF RCS_ENA = 1
RCS         EQU     $80   	; READ COMMAND SUPPORTED
  ELSE
RCS         EQU     0     	; READ COMMAND unSUPPORTED
  ENDIF

VER_NUM     EQU     $06   	; FC protocol version number (S08 long)
                            ; same as protocol version 2
                            ; except that Erase block is not
                            ; sized as power of two, just for compatibility
                            ; reasons ie. this bootloader will abort if used
                            ; with old version of hc08sprg.exe (that does not yet
                            ; support this 'non-binary' page sizes)
                            ; plus it has 24 bits addressing
IDENTS      MACRO

         IFDEF EEPROM
			      DC.B	'DZ'
			   ELSE
			      DC.B	'DV'
			   ENDIF

          IF SIZE = 96
            DC.B     '96'    ; 96kB string
          ENDIF
          IF SIZE = 128
            DC.B     '128'   ; 128kB string
          ENDIF

          IFDEF IRQOPTION
            DC.B     '-irq'     ; IRQ option used
          ENDIF

            DC.B    0
            ENDM

ERBLK_LEN	EQU		512
WRBLK_LEN	EQU		128      

ADDR24  MACRO
          DC.B  (\1) / $10000
          DC.W  (\1) & $0FFFF
        ENDM

         IFDEF EEPROM
EEP_BEG		EQU		$3C00   ; EEPROM #0 block start
EEP_END   EQU   $4000   ; EEPROM page 0 end
                        ; EEPROM page 1 is $10000 higher
         ENDIF
   
REL_VECT	EQU 	$DF90	; newly relocated int. vectors


INT_VECT	EQU		$FF90	; start of table of original vectros!


			XDEF	main
;*******************************************************************************************
  
WR_DATA		EQU	    'W'
RD_DATA		EQU	    'R'
ENDPRG		EQU	    'Q'
ERASE	  	EQU	    'E'
ACK		    EQU	    $FC
IDENT		  EQU	    'I'

T100MS		EQU	    255

ILOP        MACRO
            DC.B    $8d             ; this is illegal operation code
            ENDM
;*******************************************************************************************
MY_ZEROPAGE:	SECTION  SHORT

ADRS: 	DS.W	1
ADRR: 	DS.W	1
LEN:  	DS.B	1
STAT: 	DS.B	1
STACK:	DS.W	1

DEFAULT_RAM:    SECTION

DATA:	  DS.B	WRBLK_LEN

;*******************************************************************************************
DEFAULT_ROM:	SECTION
     
ID_STRING:
          IF SIZE = 96
		    DC.B	4				    ; number of Flash blocks
        ADDR24  ROMStart  ; START ADDRESS OF FLASH	
        ADDR24  REL_VECT  ; END ADDRESS OF FLASH																						    
        ADDR24  PPAGE_2Start
        ADDR24  PPAGE_2End+1
        ADDR24  PPAGE_4Start
        ADDR24  PPAGE_4End+1 
        ADDR24  PPAGE_5Start
        ADDR24  PPAGE_5End+1 
          ENDIF

          IF SIZE = 128
		    DC.B	6				    ; number of Flash blocks
        ADDR24  ROMStart  ; START ADDRESS OF FLASH	
        ADDR24  REL_VECT  ; END ADDRESS OF FLASH																						    
        ADDR24  PPAGE_2Start
        ADDR24  PPAGE_2End+1
        ADDR24  PPAGE_4Start
        ADDR24  PPAGE_4End+1 
        ADDR24  PPAGE_5Start
        ADDR24  PPAGE_5End+1 
        ADDR24  PPAGE_6Start
        ADDR24  PPAGE_6End+1 
        ADDR24  PPAGE_7Start
        ADDR24  PPAGE_7End+1 
          ENDIF

		    DC.W	REL_VECT		; POINTER TO APPLICATION VECTOR TABLE
        DC.W	INT_VECT		; POINTER TO BEGINING OF FLASH INT. VECTORS
        DC.W	ERBLK_LEN		; ERASE BLCK LENGTH OF FLASH ALG.
        DC.W	WRBLK_LEN		; WRITE BLCK LENGTH OF FLASH ALG.

		IDENTS
ID_STRING_END:


;*******************************************************************************************
NVPROT_ROM:		SECTION
MY_NVPROT	  DC.B	%00111101 ; flash protected & redirected (from 0xE000), this is a smallest block on DZ128 :(

NVOPT_ROM:		SECTION
MY_NVOPT	  DC.B	%00100010	; backdoor enable, redirection enable, (un)secured flash [last 10], 8 byte EEPROM

DEFAULT_ROM:	SECTION
;*******************************************************************************************
main:
    IFDEF IRQOPTION
        BIH     PVEC0                   ; if IRQ high, jump directly to real app.
    ENDIF
        LDA     SRS                     ; fetch RESET status reg.
        TSTA                            ; check if zero (this happens if RESET pulse is too short)
        BEQ     slfprg                  ; if so, jump to self programming                
        AND     #%11000000              ; mask only POR and PIN RESET source      
        BNE     slfprg                  ; any of these sources, go to self programming
PVEC0:  		
    		LDHX  	#(REL_VECT|$00FF)&$FFFE	; there should be relocated reset vector of the new app.
    		LDA	  	,X
    		PSHA
    		AND	  	1,X
    		LDX	  	1,X
    		PULH
    		INCA
    		BEQ	  	slfprg					        ; don't jump if empty vector
        JMP     ,X						          ; jump to relocated application

slfprg:        
        LDA     NVMCGTRM
        STA     MCGTRM

        LDA     NVFTRIM
        ORA     MCGSC
        STA     MCGSC

    		LDA	  	#%00000000
    		STA	  	SOPT1					; COP disable, SCI2PS as needed
    		
				; f(BUS) defaults to 16MHz
				
    		LDA		  FSTAT
    		ORA	  	#mFSTAT_FACCERR				                
    		STA	  	FSTAT					; clear any FACCERR flag

        LDA	  	#39						; div by 39+1 to fit into 150-200kHz Flash clock
        STA		  FCDIV
        
        MOV     #%00001100,SCC2  		; transmit & receive enable
    		CLR	  	SCIBDH

	  IFNDEF HISPEED
    		MOV	  	#52, SCIBDL				; BUS (8M)/(16 * 52) = 9600Bd