mc9s08dz128.inc

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

APCTL2_ADPC12:      equ    4                                         ; ADC Pin Control 12 - ADPC12 is used to control the pin associated with channel AD12
APCTL2_ADPC13:      equ    5                                         ; ADC Pin Control 13 - ADPC13 is used to control the pin associated with channel AD13
APCTL2_ADPC14:      equ    6                                         ; ADC Pin Control 14 - ADPC14 is used to control the pin associated with channel AD14
APCTL2_ADPC15:      equ    7                                         ; ADC Pin Control 15 - ADPC15 is used to control the pin associated with channel AD15
; bit position masks
mAPCTL2_ADPC8:      equ    %00000001
mAPCTL2_ADPC9:      equ    %00000010
mAPCTL2_ADPC10:     equ    %00000100
mAPCTL2_ADPC11:     equ    %00001000
mAPCTL2_ADPC12:     equ    %00010000
mAPCTL2_ADPC13:     equ    %00100000
mAPCTL2_ADPC14:     equ    %01000000
mAPCTL2_ADPC15:     equ    %10000000


;*** APCTL3 - Pin Control 3 Register; 0x00000019 ***
APCTL3:             equ    $00000019                                ;*** APCTL3 - Pin Control 3 Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL3_ADPC16:      equ    0                                         ; ADC Pin Control 16 - ADPC16 is used to control the pin associated with channel AD16
APCTL3_ADPC17:      equ    1                                         ; ADC Pin Control 17 - ADPC17 is used to control the pin associated with channel AD17
APCTL3_ADPC18:      equ    2                                         ; ADC Pin Control 18 - ADPC18 is used to control the pin associated with channel AD18
APCTL3_ADPC19:      equ    3                                         ; ADC Pin Control 19 - ADPC19 is used to control the pin associated with channel AD19
APCTL3_ADPC20:      equ    4                                         ; ADC Pin Control 20 - ADPC20 is used to control the pin associated with channel AD20
APCTL3_ADPC21:      equ    5                                         ; ADC Pin Control 21 - ADPC21 is used to control the pin associated with channel AD21
APCTL3_ADPC22:      equ    6                                         ; ADC Pin Control 22 - ADPC22 is used to control the pin associated with channel AD22
APCTL3_ADPC23:      equ    7                                         ; ADC Pin Control 23 - ADPC23 is used to control the pin associated with channel AD23
; bit position masks
mAPCTL3_ADPC16:     equ    %00000001
mAPCTL3_ADPC17:     equ    %00000010
mAPCTL3_ADPC18:     equ    %00000100
mAPCTL3_ADPC19:     equ    %00001000
mAPCTL3_ADPC20:     equ    %00010000
mAPCTL3_ADPC21:     equ    %00100000
mAPCTL3_ADPC22:     equ    %01000000
mAPCTL3_ADPC23:     equ    %10000000


;*** IRQSC - Interrupt request status and control register; 0x0000001C ***
IRQSC:              equ    $0000001C                                ;*** IRQSC - Interrupt request status and control register; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
IRQSC_IRQMOD:       equ    0                                         ; IRQ Detection Mode
IRQSC_IRQIE:        equ    1                                         ; IRQ Interrupt Enable
IRQSC_IRQACK:       equ    2                                         ; IRQ Acknowledge
IRQSC_IRQF:         equ    3                                         ; IRQ Flag
IRQSC_IRQPE:        equ    4                                         ; IRQ Pin Enable
IRQSC_IRQEDG:       equ    5                                         ; IRQ Edge Select
IRQSC_IRQPDD:       equ    6                                         ; IRQ Pull Device Disable
; bit position masks
mIRQSC_IRQMOD:      equ    %00000001
mIRQSC_IRQIE:       equ    %00000010
mIRQSC_IRQACK:      equ    %00000100
mIRQSC_IRQF:        equ    %00001000
mIRQSC_IRQPE:       equ    %00010000
mIRQSC_IRQEDG:      equ    %00100000
mIRQSC_IRQPDD:      equ    %01000000


;*** TPM1SC - TPM1 Status and Control Register; 0x00000020 ***
TPM1SC:             equ    $00000020                                ;*** TPM1SC - TPM1 Status and Control Register; 0x00000020 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1SC_PS0:         equ    0                                         ; Prescale Divisor Select Bit 0
TPM1SC_PS1:         equ    1                                         ; Prescale Divisor Select Bit 1
TPM1SC_PS2:         equ    2                                         ; Prescale Divisor Select Bit 2
TPM1SC_CLKSA:       equ    3                                         ; Clock Source Select A
TPM1SC_CLKSB:       equ    4                                         ; Clock Source Select B
TPM1SC_CPWMS:       equ    5                                         ; Center-Aligned PWM Select
TPM1SC_TOIE:        equ    6                                         ; Timer Overflow Interrupt Enable
TPM1SC_TOF:         equ    7                                         ; Timer Overflow Flag
; bit position masks
mTPM1SC_PS0:        equ    %00000001
mTPM1SC_PS1:        equ    %00000010
mTPM1SC_PS2:        equ    %00000100
mTPM1SC_CLKSA:      equ    %00001000
mTPM1SC_CLKSB:      equ    %00010000
mTPM1SC_CPWMS:      equ    %00100000
mTPM1SC_TOIE:       equ    %01000000
mTPM1SC_TOF:        equ    %10000000


;*** TPM1CNT - TPM1 Timer Counter Register; 0x00000021 ***
TPM1CNT:            equ    $00000021                                ;*** TPM1CNT - TPM1 Timer Counter Register; 0x00000021 ***


;*** TPM1CNTH - TPM1 Timer Counter Register High; 0x00000021 ***
TPM1CNTH:           equ    $00000021                                ;*** TPM1CNTH - TPM1 Timer Counter Register High; 0x00000021 ***


;*** TPM1CNTL - TPM1 Timer Counter Register Low; 0x00000022 ***
TPM1CNTL:           equ    $00000022                                ;*** TPM1CNTL - TPM1 Timer Counter Register Low; 0x00000022 ***


;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0x00000023 ***
TPM1MOD:            equ    $00000023                                ;*** TPM1MOD - TPM1 Timer Counter Modulo Register; 0x00000023 ***


;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0x00000023 ***
TPM1MODH:           equ    $00000023                                ;*** TPM1MODH - TPM1 Timer Counter Modulo Register High; 0x00000023 ***


;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0x00000024 ***
TPM1MODL:           equ    $00000024                                ;*** TPM1MODL - TPM1 Timer Counter Modulo Register Low; 0x00000024 ***


;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000025 ***
TPM1C0SC:           equ    $00000025                                ;*** TPM1C0SC - TPM1 Timer Channel 0 Status and Control Register; 0x00000025 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C0SC_ELS0A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C0SC_ELS0B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C0SC_MS0A:      equ    4                                         ; Mode Select A for TPM Channel 0
TPM1C0SC_MS0B:      equ    5                                         ; Mode Select B for TPM Channel 0
TPM1C0SC_CH0IE:     equ    6                                         ; Channel 0 Interrupt Enable
TPM1C0SC_CH0F:      equ    7                                         ; Channel 0 Flag
; bit position masks
mTPM1C0SC_ELS0A:    equ    %00000100
mTPM1C0SC_ELS0B:    equ    %00001000
mTPM1C0SC_MS0A:     equ    %00010000
mTPM1C0SC_MS0B:     equ    %00100000
mTPM1C0SC_CH0IE:    equ    %01000000
mTPM1C0SC_CH0F:     equ    %10000000


;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0x00000026 ***
TPM1C0V:            equ    $00000026                                ;*** TPM1C0V - TPM1 Timer Channel 0 Value Register; 0x00000026 ***


;*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0x00000026 ***
TPM1C0VH:           equ    $00000026                                ;*** TPM1C0VH - TPM1 Timer Channel 0 Value Register High; 0x00000026 ***


;*** TPM1C0VL - TPM1 Timer Channel 0 Value Register Low; 0x00000027 ***
TPM1C0VL:           equ    $00000027                                ;*** TPM1C0VL - TPM1 Timer Channel 0 Value Register Low; 0x00000027 ***


;*** TPM1C1SC - TPM1 Timer Channel 1 Status and Control Register; 0x00000028 ***
TPM1C1SC:           equ    $00000028                                ;*** TPM1C1SC - TPM1 Timer Channel 1 Status and Control Register; 0x00000028 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C1SC_ELS1A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C1SC_ELS1B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C1SC_MS1A:      equ    4                                         ; Mode Select A for TPM Channel 1
TPM1C1SC_MS1B:      equ    5                                         ; Mode Select B for TPM Channel 1
TPM1C1SC_CH1IE:     equ    6                                         ; Channel 1 Interrupt Enable
TPM1C1SC_CH1F:      equ    7                                         ; Channel 1 Flag
; bit position masks
mTPM1C1SC_ELS1A:    equ    %00000100
mTPM1C1SC_ELS1B:    equ    %00001000
mTPM1C1SC_MS1A:     equ    %00010000
mTPM1C1SC_MS1B:     equ    %00100000
mTPM1C1SC_CH1IE:    equ    %01000000
mTPM1C1SC_CH1F:     equ    %10000000


;*** TPM1C1V - TPM1 Timer Channel 1 Value Register; 0x00000029 ***
TPM1C1V:            equ    $00000029                                ;*** TPM1C1V - TPM1 Timer Channel 1 Value Register; 0x00000029 ***


;*** TPM1C1VH - TPM1 Timer Channel 1 Value Register High; 0x00000029 ***
TPM1C1VH:           equ    $00000029                                ;*** TPM1C1VH - TPM1 Timer Channel 1 Value Register High; 0x00000029 ***


;*** TPM1C1VL - TPM1 Timer Channel 1 Value Register Low; 0x0000002A ***
TPM1C1VL:           equ    $0000002A                                ;*** TPM1C1VL - TPM1 Timer Channel 1 Value Register Low; 0x0000002A ***


;*** TPM1C2SC - TPM1 Timer Channel 2 Status and Control Register; 0x0000002B ***
TPM1C2SC:           equ    $0000002B                                ;*** TPM1C2SC - TPM1 Timer Channel 2 Status and Control Register; 0x0000002B ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C2SC_ELS2A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C2SC_ELS2B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C2SC_MS2A:      equ    4                                         ; Mode Select A for TPM Channel 2
TPM1C2SC_MS2B:      equ    5                                         ; Mode Select B for TPM Channel 2
TPM1C2SC_CH2IE:     equ    6                                         ; Channel 2 Interrupt Enable
TPM1C2SC_CH2F:      equ    7                                         ; Channel 2 Flag
; bit position masks
mTPM1C2SC_ELS2A:    equ    %00000100
mTPM1C2SC_ELS2B:    equ    %00001000
mTPM1C2SC_MS2A:     equ    %00010000
mTPM1C2SC_MS2B:     equ    %00100000
mTPM1C2SC_CH2IE:    equ    %01000000
mTPM1C2SC_CH2F:     equ    %10000000


;*** TPM1C2V - TPM1 Timer Channel 2 Value Register; 0x0000002C ***
TPM1C2V:            equ    $0000002C                                ;*** TPM1C2V - TPM1 Timer Channel 2 Value Register; 0x0000002C ***


;*** TPM1C2VH - TPM1 Timer Channel 2 Value Register High; 0x0000002C ***
TPM1C2VH:           equ    $0000002C                                ;*** TPM1C2VH - TPM1 Timer Channel 2 Value Register High; 0x0000002C ***


;*** TPM1C2VL - TPM1 Timer Channel 2 Value Register Low; 0x0000002D ***
TPM1C2VL:           equ    $0000002D                                ;*** TPM1C2VL - TPM1 Timer Channel 2 Value Register Low; 0x0000002D ***


;*** TPM1C3SC - TPM1 Timer Channel 3 Status and Control Register; 0x0000002E ***
TPM1C3SC:           equ    $0000002E                                ;*** TPM1C3SC - TPM1 Timer Channel 3 Status and Control Register; 0x0000002E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
TPM1C3SC_ELS3A:     equ    2                                         ; Edge/Level Select Bit A
TPM1C3SC_ELS3B:     equ    3                                         ; Edge/Level Select Bit B
TPM1C3SC_MS3A:      equ    4                                         ; Mode Select A for TPM Channel 3
TPM1C3SC_MS3B:      equ    5                                         ; Mode Select B for TPM Channel 3
TPM1C3SC_CH3IE:     equ    6                                         ; Channel 3 Interrupt Enable
TPM1C3SC_CH3F:      equ    7                                         ; Channel 3 Flag
; bit position masks
mTPM1C3SC_ELS3A:    equ    %00000100
mTPM1C3SC_ELS3B:    equ    %00001000
mTPM1C3SC_MS3A:     equ    %00010000
mTPM1C3SC_MS3B:     equ    %00100000
mTPM1C3SC_CH3IE:    equ    %01000000
mTPM1C3SC_CH3F:     equ    %10000000


;*** TPM1C3V - TPM1 Timer Channel 3 Value Register; 0x0000002F ***
TPM1C3V:            equ    $0000002F                                ;*** TPM1C3V - TPM1 Timer Channel 3 Value Register; 0x0000002F ***


;*** TPM1C3VH - TPM1 Timer Channel 3 Value Register High; 0x0000002F ***
TPM1C3VH:           equ    $0000002F                                ;*** TPM1C3VH - TPM1 Timer Channel 3 Value Register High; 0x0000002F ***


;*** TPM1C3VL - TPM1 Timer Channel 3 Value Register Low; 0x00000030 ***