📄 mc9s08dz128.inc
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mPTGDD_PTGDD1: equ %00000010
mPTGDD_PTGDD2: equ %00000100
mPTGDD_PTGDD3: equ %00001000
mPTGDD_PTGDD4: equ %00010000
mPTGDD_PTGDD5: equ %00100000
mPTGDD_PTGDD6: equ %01000000
mPTGDD_PTGDD7: equ %10000000
;*** ACMP1SC - ACMP1 Status and Control Register; 0x0000000E ***
ACMP1SC: equ $0000000E ;*** ACMP1SC - ACMP1 Status and Control Register; 0x0000000E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP1SC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMP1SC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMP1SC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMP1SC_ACO: equ 3 ; Analog Comparator Output
ACMP1SC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMP1SC_ACF: equ 5 ; Analog Comparator Flag
ACMP1SC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMP1SC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMP1SC_ACMOD0: equ %00000001
mACMP1SC_ACMOD1: equ %00000010
mACMP1SC_ACOPE: equ %00000100
mACMP1SC_ACO: equ %00001000
mACMP1SC_ACIE: equ %00010000
mACMP1SC_ACF: equ %00100000
mACMP1SC_ACBGS: equ %01000000
mACMP1SC_ACME: equ %10000000
;*** ACMP2SC - ACMP2 Status and Control Register; 0x0000000F ***
ACMP2SC: equ $0000000F ;*** ACMP2SC - ACMP2 Status and Control Register; 0x0000000F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMP2SC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMP2SC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMP2SC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMP2SC_ACO: equ 3 ; Analog Comparator Output
ACMP2SC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMP2SC_ACF: equ 5 ; Analog Comparator Flag
ACMP2SC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMP2SC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMP2SC_ACMOD0: equ %00000001
mACMP2SC_ACMOD1: equ %00000010
mACMP2SC_ACOPE: equ %00000100
mACMP2SC_ACO: equ %00001000
mACMP2SC_ACIE: equ %00010000
mACMP2SC_ACF: equ %00100000
mACMP2SC_ACBGS: equ %01000000
mACMP2SC_ACME: equ %10000000
;*** ADCSC1 - Status and Control Register 1; 0x00000010 ***
ADCSC1: equ $00000010 ;*** ADCSC1 - Status and Control Register 1; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCSC1_ADCH0: equ 0 ; Input Channel Select Bit 0
ADCSC1_ADCH1: equ 1 ; Input Channel Select Bit 1
ADCSC1_ADCH2: equ 2 ; Input Channel Select Bit 2
ADCSC1_ADCH3: equ 3 ; Input Channel Select Bit 3
ADCSC1_ADCH4: equ 4 ; Input Channel Select Bit 4
ADCSC1_ADCO: equ 5 ; Continuous Conversion Enable - ADCO is used to enable continuous conversions
ADCSC1_AIEN: equ 6 ; Interrupt Enable - AIEN is used to enable conversion complete interrupts. When COCO becomes set while AIEN is high, an interrupt is asserted
ADCSC1_COCO: equ 7 ; Conversion Complete Flag
; bit position masks
mADCSC1_ADCH0: equ %00000001
mADCSC1_ADCH1: equ %00000010
mADCSC1_ADCH2: equ %00000100
mADCSC1_ADCH3: equ %00001000
mADCSC1_ADCH4: equ %00010000
mADCSC1_ADCO: equ %00100000
mADCSC1_AIEN: equ %01000000
mADCSC1_COCO: equ %10000000
;*** ADCSC2 - Status and Control Register 2; 0x00000011 ***
ADCSC2: equ $00000011 ;*** ADCSC2 - Status and Control Register 2; 0x00000011 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCSC2_ACFGT: equ 4 ; Compare Function Greater Than Enable
ADCSC2_ACFE: equ 5 ; Compare Function Enable - ACFE is used to enable the compare function
ADCSC2_ADTRG: equ 6 ; Conversion Trigger Select-ADTRG is used to select the type of trigger to be used for initiating a conversion
ADCSC2_ADACT: equ 7 ; Conversion Active - ADACT indicates that a conversion is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted
; bit position masks
mADCSC2_ACFGT: equ %00010000
mADCSC2_ACFE: equ %00100000
mADCSC2_ADTRG: equ %01000000
mADCSC2_ADACT: equ %10000000
;*** ADCR - Data Result Register; 0x00000012 ***
ADCR: equ $00000012 ;*** ADCR - Data Result Register; 0x00000012 ***
;*** ADCRH - Data Result High Register; 0x00000012 ***
ADCRH: equ $00000012 ;*** ADCRH - Data Result High Register; 0x00000012 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCRH_ADR8: equ 0 ; ADC Result Data Bit 8
ADCRH_ADR9: equ 1 ; ADC Result Data Bit 9
ADCRH_ADR10: equ 2 ; ADC Result Data Bit 10
ADCRH_ADR11: equ 3 ; ADC Result Data Bit 11
; bit position masks
mADCRH_ADR8: equ %00000001
mADCRH_ADR9: equ %00000010
mADCRH_ADR10: equ %00000100
mADCRH_ADR11: equ %00001000
;*** ADCRL - Data Result Low Register; 0x00000013 ***
ADCRL: equ $00000013 ;*** ADCRL - Data Result Low Register; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCRL_ADR0: equ 0 ; ADC Result Data Bit 0
ADCRL_ADR1: equ 1 ; ADC Result Data Bit 1
ADCRL_ADR2: equ 2 ; ADC Result Data Bit 2
ADCRL_ADR3: equ 3 ; ADC Result Data Bit 3
ADCRL_ADR4: equ 4 ; ADC Result Data Bit 4
ADCRL_ADR5: equ 5 ; ADC Result Data Bit 5
ADCRL_ADR6: equ 6 ; ADC Result Data Bit 6
ADCRL_ADR7: equ 7 ; ADC Result Data Bit 7
; bit position masks
mADCRL_ADR0: equ %00000001
mADCRL_ADR1: equ %00000010
mADCRL_ADR2: equ %00000100
mADCRL_ADR3: equ %00001000
mADCRL_ADR4: equ %00010000
mADCRL_ADR5: equ %00100000
mADCRL_ADR6: equ %01000000
mADCRL_ADR7: equ %10000000
;*** ADCCV - Compare Value Register; 0x00000014 ***
ADCCV: equ $00000014 ;*** ADCCV - Compare Value Register; 0x00000014 ***
;*** ADCCVH - Compare Value High Register; 0x00000014 ***
ADCCVH: equ $00000014 ;*** ADCCVH - Compare Value High Register; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCVH_ADCV8: equ 0 ; Compare Function Value 8
ADCCVH_ADCV9: equ 1 ; Compare Function Value 9
ADCCVH_ADCV10: equ 2 ; Compare Function Value 10
ADCCVH_ADCV11: equ 3 ; Compare Function Value 11
; bit position masks
mADCCVH_ADCV8: equ %00000001
mADCCVH_ADCV9: equ %00000010
mADCCVH_ADCV10: equ %00000100
mADCCVH_ADCV11: equ %00001000
;*** ADCCVL - Compare Value Low Register; 0x00000015 ***
ADCCVL: equ $00000015 ;*** ADCCVL - Compare Value Low Register; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCVL_ADCV0: equ 0 ; Compare Function Value 0
ADCCVL_ADCV1: equ 1 ; Compare Function Value 1
ADCCVL_ADCV2: equ 2 ; Compare Function Value 2
ADCCVL_ADCV3: equ 3 ; Compare Function Value 3
ADCCVL_ADCV4: equ 4 ; Compare Function Value 4
ADCCVL_ADCV5: equ 5 ; Compare Function Value 5
ADCCVL_ADCV6: equ 6 ; Compare Function Value 6
ADCCVL_ADCV7: equ 7 ; Compare Function Value 7
; bit position masks
mADCCVL_ADCV0: equ %00000001
mADCCVL_ADCV1: equ %00000010
mADCCVL_ADCV2: equ %00000100
mADCCVL_ADCV3: equ %00001000
mADCCVL_ADCV4: equ %00010000
mADCCVL_ADCV5: equ %00100000
mADCCVL_ADCV6: equ %01000000
mADCCVL_ADCV7: equ %10000000
;*** ADCCFG - Configuration Register; 0x00000016 ***
ADCCFG: equ $00000016 ;*** ADCCFG - Configuration Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ADCCFG_ADICLK0: equ 0 ; Input Clock Select Bit 0
ADCCFG_ADICLK1: equ 1 ; Input Clock Select Bit 1
ADCCFG_MODE0: equ 2 ; Conversion Mode Selection Bit 0
ADCCFG_MODE1: equ 3 ; Conversion Mode Selection Bit 1
ADCCFG_ADLSMP: equ 4 ; Long Sample Time Configuration
ADCCFG_ADIV0: equ 5 ; Clock Divide Select Bit 0
ADCCFG_ADIV1: equ 6 ; Clock Divide Select Bit 1
ADCCFG_ADLPC: equ 7 ; Low Power Configuration
; bit position masks
mADCCFG_ADICLK0: equ %00000001
mADCCFG_ADICLK1: equ %00000010
mADCCFG_MODE0: equ %00000100
mADCCFG_MODE1: equ %00001000
mADCCFG_ADLSMP: equ %00010000
mADCCFG_ADIV0: equ %00100000
mADCCFG_ADIV1: equ %01000000
mADCCFG_ADLPC: equ %10000000
;*** APCTL1 - Pin Control 1 Register; 0x00000017 ***
APCTL1: equ $00000017 ;*** APCTL1 - Pin Control 1 Register; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL1_ADPC0: equ 0 ; ADC Pin Control 0 - ADPC0 is used to control the pin associated with channel AD0
APCTL1_ADPC1: equ 1 ; ADC Pin Control 1 - ADPC1 is used to control the pin associated with channel AD1
APCTL1_ADPC2: equ 2 ; ADC Pin Control 2 - ADPC2 is used to control the pin associated with channel AD2
APCTL1_ADPC3: equ 3 ; ADC Pin Control 3 - ADPC3 is used to control the pin associated with channel AD3
APCTL1_ADPC4: equ 4 ; ADC Pin Control 4 - ADPC4 is used to control the pin associated with channel AD4
APCTL1_ADPC5: equ 5 ; ADC Pin Control 5 - ADPC5 is used to control the pin associated with channel AD5
APCTL1_ADPC6: equ 6 ; ADC Pin Control 6 - ADPC6 is used to control the pin associated with channel AD6
APCTL1_ADPC7: equ 7 ; ADC Pin Control 7 - ADPC7 is used to control the pin associated with channel AD7
; bit position masks
mAPCTL1_ADPC0: equ %00000001
mAPCTL1_ADPC1: equ %00000010
mAPCTL1_ADPC2: equ %00000100
mAPCTL1_ADPC3: equ %00001000
mAPCTL1_ADPC4: equ %00010000
mAPCTL1_ADPC5: equ %00100000
mAPCTL1_ADPC6: equ %01000000
mAPCTL1_ADPC7: equ %10000000
;*** APCTL2 - Pin Control 2 Register; 0x00000018 ***
APCTL2: equ $00000018 ;*** APCTL2 - Pin Control 2 Register; 0x00000018 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
APCTL2_ADPC8: equ 0 ; ADC Pin Control 8 - ADPC8 is used to control the pin associated with channel AD8
APCTL2_ADPC9: equ 1 ; ADC Pin Control 9 - ADPC9 is used to control the pin associated with channel AD9
APCTL2_ADPC10: equ 2 ; ADC Pin Control 10 - ADPC10 is used to control the pin associated with channel AD10
APCTL2_ADPC11: equ 3 ; ADC Pin Control 11 - ADPC11 is used to control the pin associated with channel AD11
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