📄 mc9s08dz128.inc
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; Based on CPU DB MC9S08DZ128_100, version 3.00.023 (RegistersPrg V2.23)
; ###################################################################
; Filename : mc9s08dz128.inc
; Processor : MC9S08DZ128CLL
; FileFormat: V2.23
; DataSheet : MC9S08DZ128 Rev. 1 Draft H 04/2007
; Compiler : CodeWarrior compiler
; Date/Time : 26.2.2008, 11:39
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2008
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; CPU Registers Revisions:
; - none
;
; File-Format-Revisions:
; - 19.07.2007, V2.18 :
; - Improved number of blanked lines inside register structures
; - 06.08.2007, V2.19 :
; - CPUDB revisions generated ahead of the file-format revisions.
; - 11.09.2007, V2.20 :
; - Added comment about initialization of unbonded pins.
; - 02.01.2008, V2.21 :
; - Changes have not affected this file (because they are related to another family)
; - 13.02.2008, V2.22 :
; - Changes have not affected this file (because they are related to another family)
; - 20.02.2008, V2.23 :
; - Changes have not affected this file (because they are related to another family)
;
; Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
; derivative device. To avoid extra current drain from floating input pins, the user抯 reset
; initialization routine in the application program must either enable on-chip pull-up devices
; or change the direction of unconnected pins to outputs so the pins do not float.
; ###################################################################
;*** Memory Map and Interrupt Vectors
;******************************************
ROMStart: equ $00004000
ROMEnd: equ $00007FFF
Z_RAMStart: equ $00000080
Z_RAMEnd: equ $000000FF
RAMStart: equ $00000100
RAMEnd: equ $000017FF
RAM1Start: equ $00001900
RAM1End: equ $0000217F
ROM1Start: equ $00002180
ROM1End: equ $00003BFF
ROM2Start: equ $0000C000
ROM2End: equ $0000FF7F
PPAGE_0Start: equ $00008000
PPAGE_0End: equ $0000A17F
PPAGE_0_1Start: equ $0000BC00
PPAGE_0_1End: equ $0000BFFF
PPAGE_2Start: equ $00028000
PPAGE_2End: equ $0002BFFF
PPAGE_4Start: equ $00048000
PPAGE_4End: equ $0004BFFF
PPAGE_5Start: equ $00058000
PPAGE_5End: equ $0005BFFF
PPAGE_6Start: equ $00068000
PPAGE_6End: equ $0006BFFF
PPAGE_7Start: equ $00078000
PPAGE_7End: equ $0007BFFF
EEPROMStart: equ $00003C00
EEPROMEnd: equ $00003FFF
;
VReserved63: equ $0000FF80
VReserved62: equ $0000FF82
VReserved61: equ $0000FF84
VReserved60: equ $0000FF86
VReserved59: equ $0000FF88
VReserved58: equ $0000FF8A
VReserved57: equ $0000FF8C
VReserved56: equ $0000FF8E
Vportj: equ $0000FF90
Viic2: equ $0000FF92
Vspi2: equ $0000FF94
Vtpm3ovf: equ $0000FF96
Vtpm3ch3: equ $0000FF98
Vtpm3ch2: equ $0000FF9A
Vtpm3ch1: equ $0000FF9C
Vtpm3ch0: equ $0000FF9E
VReserved47: equ $0000FFA0
VReserved46: equ $0000FFA2
VReserved45: equ $0000FFA4
VReserved44: equ $0000FFA6
VReserved43: equ $0000FFA8
VReserved42: equ $0000FFAA
VReserved41: equ $0000FFAC
VReserved40: equ $0000FFAE
VReserved39: equ $0000FFB0
VReserved38: equ $0000FFB2
VReserved37: equ $0000FFB4
VReserved36: equ $0000FFB6
VReserved35: equ $0000FFB8
VReserved34: equ $0000FFBA
VReserved33: equ $0000FFBC
VReserved32: equ $0000FFBE
Vacmp2: equ $0000FFC0
Vacmp1: equ $0000FFC2
Vcantx: equ $0000FFC4
Vcanrx: equ $0000FFC6
Vcanerr: equ $0000FFC8
Vcanwu: equ $0000FFCA
Vrtc: equ $0000FFCC
Viic1: equ $0000FFCE
Vadc: equ $0000FFD0
Vport: equ $0000FFD2
Vsci2tx: equ $0000FFD4
Vsci2rx: equ $0000FFD6
Vsci2err: equ $0000FFD8
Vsci1tx: equ $0000FFDA
Vsci1rx: equ $0000FFDC
Vsci1err: equ $0000FFDE
Vspi1: equ $0000FFE0
Vtpm2ovf: equ $0000FFE2
Vtpm2ch1: equ $0000FFE4
Vtpm2ch0: equ $0000FFE6
Vtpm1ovf: equ $0000FFE8
Vtpm1ch5: equ $0000FFEA
Vtpm1ch4: equ $0000FFEC
Vtpm1ch3: equ $0000FFEE
Vtpm1ch2: equ $0000FFF0
Vtpm1ch1: equ $0000FFF2
Vtpm1ch0: equ $0000FFF4
Vlol: equ $0000FFF6
Vlvd: equ $0000FFF8
Virq: equ $0000FFFA
Vswi: equ $0000FFFC
Vreset: equ $0000FFFE
;
;*** PTAD - Port A Data Register; 0x00000000 ***
PTAD: equ $00000000 ;*** PTAD - Port A Data Register; 0x00000000 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0
PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1
PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2
PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3
PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4
PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5
PTAD_PTAD6: equ 6 ; Port A Data Register Bit 6
PTAD_PTAD7: equ 7 ; Port A Data Register Bit 7
; bit position masks
mPTAD_PTAD0: equ %00000001
mPTAD_PTAD1: equ %00000010
mPTAD_PTAD2: equ %00000100
mPTAD_PTAD3: equ %00001000
mPTAD_PTAD4: equ %00010000
mPTAD_PTAD5: equ %00100000
mPTAD_PTAD6: equ %01000000
mPTAD_PTAD7: equ %10000000
;*** PTADD - Port A Data Direction Register; 0x00000001 ***
PTADD: equ $00000001 ;*** PTADD - Port A Data Direction Register; 0x00000001 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0
PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1
PTADD_PTADD2: equ 2 ; Data Direction for Port A Bit 2
PTADD_PTADD3: equ 3 ; Data Direction for Port A Bit 3
PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4
PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5
PTADD_PTADD6: equ 6 ; Data Direction for Port A Bit 6
PTADD_PTADD7: equ 7 ; Data Direction for Port A Bit 7
; bit position masks
mPTADD_PTADD0: equ %00000001
mPTADD_PTADD1: equ %00000010
mPTADD_PTADD2: equ %00000100
mPTADD_PTADD3: equ %00001000
mPTADD_PTADD4: equ %00010000
mPTADD_PTADD5: equ %00100000
mPTADD_PTADD6: equ %01000000
mPTADD_PTADD7: equ %10000000
;*** PTBD - Port B Data Register; 0x00000002 ***
PTBD: equ $00000002 ;*** PTBD - Port B Data Register; 0x00000002 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBD_PTBD0: equ 0 ; Port B Data Register Bit 0
PTBD_PTBD1: equ 1 ; Port B Data Register Bit 1
PTBD_PTBD2: equ 2 ; Port B Data Register Bit 2
PTBD_PTBD3: equ 3 ; Port B Data Register Bit 3
PTBD_PTBD4: equ 4 ; Port B Data Register Bit 4
PTBD_PTBD5: equ 5 ; Port B Data Register Bit 5
PTBD_PTBD6: equ 6 ; Port B Data Register Bit 6
PTBD_PTBD7: equ 7 ; Port B Data Register Bit 7
; bit position masks
mPTBD_PTBD0: equ %00000001
mPTBD_PTBD1: equ %00000010
mPTBD_PTBD2: equ %00000100
mPTBD_PTBD3: equ %00001000
mPTBD_PTBD4: equ %00010000
mPTBD_PTBD5: equ %00100000
mPTBD_PTBD6: equ %01000000
mPTBD_PTBD7: equ %10000000
;*** PTBDD - Port B Data Direction Register; 0x00000003 ***
PTBDD: equ $00000003 ;*** PTBDD - Port B Data Direction Register; 0x00000003 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTBDD_PTBDD0: equ 0 ; Data Direction for Port B Bit 0
PTBDD_PTBDD1: equ 1 ; Data Direction for Port B Bit 1
PTBDD_PTBDD2: equ 2 ; Data Direction for Port B Bit 2
PTBDD_PTBDD3: equ 3 ; Data Direction for Port B Bit 3
PTBDD_PTBDD4: equ 4 ; Data Direction for Port B Bit 4
PTBDD_PTBDD5: equ 5 ; Data Direction for Port B Bit 5
PTBDD_PTBDD6: equ 6 ; Data Direction for Port B Bit 6
PTBDD_PTBDD7: equ 7 ; Data Direction for Port B Bit 7
; bit position masks
mPTBDD_PTBDD0: equ %00000001
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