slfprg-s08gbgt.asm

M68HC08及HCS08系列单片机bootloader引导程序源码/示例

;*********************************************************************
; HEADER_START
;
;  	   $File Name: slfprg-s08gbgt.asm$
;      Project:        Developper's HC08 Bootloader Slave
;      Description:    S08GB/GT main bootloader file, usable also for MC1321x
;      Platform:       HCS08
;      $Version: 6.0.22.0$
;      $Date: Mar-14-2008$ 
;      $Last Modified By: r30323$
;      Company:        Freescale Semiconductor
;      Security:       General Business
;
; =================================================================== 
; Copyright (c):      Freescale Semiconductor, 2004-2007, All rights reserved.
;
; =================================================================== 
; THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY
; EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
; PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL FREESCALE OR
; ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
; STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
; OF THE POSSIBILITY OF SUCH DAMAGE.
; ===================================================================
;
; HEADER_END

; labels SCI, SIZE and IRQOPTION defined externally:
; SIZE = 8, 16, 32, 60 depending whether what memory size of GB/GT family is required
; AFAMILY, if defined, A-family compiled, actually differs only with GT16A and GT8 (FPROT/NVPROT)
; 
; IRQOPTION *NOT* defined >> regular version (bootloader starts always after POR)
; IRQOPTION defined >> using IRQ option (bootloading won't start if IRQ high)
;
; label SCI = 1, 2 selects what SCI channel is used
; label HISPEED => if defined, 115200Bd is used instead of 9600Bd

	include "9s08gb60.inc"

	IFNDEF SCI
SCI		EQU		1
	ENDIF	

	IF SCI = 1
SCIBDH	equ SCI1BDH
SCIBDL	equ SCI1BDL
SCC1  	equ SCI1C1
SCC2  	equ SCI1C2
SCC3  	equ SCI1C3
SCS1  	equ SCI1S1
SCS2  	equ SCI1S2
SCDR  	equ SCI1D

TXDDDR          EQU     PTEDD
TXDPORT         EQU     PTED
TXDBIT          EQU     0
RXDPORT         EQU     PTED
RXDBIT          EQU     1
	ENDIF

	IF SCI = 2
SCIBDH	equ SCI2BDH
SCIBDL	equ SCI2BDL
SCC1  	equ SCI2C1
SCC2  	equ SCI2C2
SCC3  	equ SCI2C3
SCS1  	equ SCI2S1
SCS2  	equ SCI2S2
SCDR  	equ SCI2D

TXDDDR          EQU     PTCDD
TXDPORT         EQU     PTCD
TXDBIT          EQU     0
RXDPORT         EQU     PTCD
RXDBIT          EQU     1
	ENDIF


RCS_ENA    	EQU     1     	; READ COMMAND SUPPORTED?

  IF RCS_ENA = 1
RCS         EQU     $80   	; READ COMMAND SUPPORTED
  ELSE
RCS         EQU     0     	; READ COMMAND unSUPPORTED
  ENDIF

VER_NUM     EQU     2     	; FC protocol version number

IDENTS      MACRO

			      DC.B	'GB/GT'

          IF SIZE = 8
            DC.B     '8'      ; 8kB string
            IFDEF AFAMILY
              DC.B     'A'      ; A-family designator
            ENDIF
          ENDIF
          IF SIZE = 16
            DC.B     '16'     ; 16kB string
            IFDEF AFAMILY
              DC.B     'A'      ; A-family designator
            ENDIF
          ENDIF
          IF SIZE = 32
            DC.B     '32(A)'     ; 32kB string
          ENDIF
          IF SIZE = 60
            DC.B     '60(A)'     ; 60kB string
          ENDIF

          IFDEF IRQOPTION
            DC.B     '-irq'   ; IRQ option used
          ENDIF

            DC.B    0
            ENDM

ERBLK_LEN	EQU		512
WRBLK_LEN	EQU		128      

        IF SIZE = 8
FLS_BEG		EQU		$E000   ; FLASH #0 block start
FLS_END		EQU		$FDC0   ; FLASH #0 block end
		    ENDIF

        IF SIZE = 16
FLS_BEG		EQU		$C000   ; FLASH #0 block start
FLS_END		EQU		$FDC0   ; FLASH #0 block end
		    ENDIF

        IF SIZE = 32
FLS_BEG		EQU		$8000   ; FLASH #0 block start
FLS_END		EQU		$FDC0   ; FLASH #0 block end
		    ENDIF

        IF SIZE = 60
FLS_BEG		EQU		$1080   ; FLASH #0 block start
FLS_END		EQU		$1800   ; FLASH #0 block end
FLS_BEG1	EQU		$182C   ; FLASH #1 block start
FLS_END1	EQU		$FDC0   ; FLASH #1 block end
		    ENDIF
		   
REL_VECT	EQU 	$FDC0	; newly relocated int. vectors

INT_VECT	EQU		$FFC0	; start of table of original vectors


			XDEF	main
;*******************************************************************************************
  
WR_DATA		EQU	    'W'
RD_DATA		EQU	    'R'
ENDPRG		EQU	    'Q'
ERASE	  	EQU	    'E'
ACK		    EQU	    $FC
IDENT		  EQU	    'I'

T100MS		EQU	    255

ILOP        MACRO
            DC.B    $8D             ; this is illegal operation code
            ENDM
;*******************************************************************************************
MY_ZEROPAGE:	SECTION  SHORT

ADRS: 	DS.W	1
ADRR: 	DS.W	1
LEN:  	DS.B	1
STAT: 	DS.B	1
STACK:	DS.W	1

DEFAULT_RAM:    SECTION

DATA:	  DS.B  	WRBLK_LEN

;*******************************************************************************************
DEFAULT_ROM:	SECTION
     
ID_STRING:
      IF (SIZE = 8) || (SIZE = 16) || (SIZE = 32)
		    DC.B	1				    ; number of Flash blocks
        DC.W	FLS_BEG     ; START ADDRESS OF FLASH	
        DC.W  FLS_END		  ; END ADDRESS OF FLASH	
		  ENDIF
      IF SIZE = 60
		    DC.B	2			    	; number of Flash blocks
        DC.W	FLS_BEG     ; START ADDRESS OF FLASH	
        DC.W  FLS_END		  ; END ADDRESS OF FLASH	
        DC.W	FLS_BEG1    ; START ADDRESS OF FLASH #2
        DC.W	FLS_END1	  ; END ADDRESS OF FLASH	 #2
		  ENDIF		  
		    DC.W	REL_VECT		; POINTER TO APPLICATION VECTOR TABLE
        DC.W	INT_VECT		; POINTER TO BEGINING OF FLASH INT. VECTORS
        DC.W	ERBLK_LEN		; ERASE BLCK LENGTH OF FLASH ALG.
        DC.W	WRBLK_LEN		; WRITE BLCK LENGTH OF FLASH ALG.

		IDENTS
ID_STRING_END:


    	XDEF 	NVPROT	
    	XDEF	NVOPT 	

;*******************************************************************************************

  IFDEF AFAMILY
    IF (SIZE = 8) || (SIZE = 16)    ;; GT8A and GT16A only
NVPROT_ROM:		SECTION
NVPROT	DC.B  $FC     	; FPDIS = 0, flash protected (from 0xFE00) 
    ELSE                            ;; other A-family
NVPROT_ROM:		SECTION
NVPROT	DC.B	%10000000	; fpopen, flash protected (from 0xFE00) 
    ENDIF
  ELSE                              ;; all non-A family
NVPROT_ROM:		SECTION
NVPROT	DC.B	%10000000	; fpopen, flash protected (from 0xFE00) 
  ENDIF


NVOPT_ROM:		SECTION
NVOPT	  DC.B	%00000010	; backdoor enable, redirection enable, (un)secured flash [last 10]

DEFAULT_ROM:	SECTION
;*******************************************************************************************
main:
    		MOV	  	#$80, ICGTRM			      ; trim to middle (+-25%) so our trim will work OK 

    IFDEF IRQOPTION
        BIH     PVEC0                   ; if IRQ high, jump directly to real app.
    ENDIF
        LDA     SRS                     ; fetch RESET status reg.
        TSTA                            ; check if zero (this happens if RESET pulse is too short)
        BEQ     slfprg                  ; if so, jump to self programming                
        AND     #%11000000              ; mask only POR and PIN RESET source      
        BNE     slfprg                  ; any of these sources, go to self programming
PVEC0:  		
    		LDHX  	#(REL_VECT|$00FF)&$FFFE	; there should be relocated reset vector of the new app.
    		LDA	  	,X
    		PSHA
    		AND	  	1,X
    		LDX	  	1,X
    		PULH
    		INCA
    		BEQ	  	slfprg					  ; don't jump if empty vector!
        JMP     ,X						    ; jump to relocated application!

slfprg:        
        BSET    TXDBIT,TXDPORT
        BSET    TXDBIT,TXDDDR     ; TxD high when SCI disabled        

    		LDA	  	#%00000010
    		STA	  	SOPT					    ; COP disable, BDM enable (for now)
        MOV	  	#%00001000,ICGC1	; FEI mode

	  IFNDEF HISPEED
        MOV	  	#%00000001,ICGC2	; N=4,R=2, f(ICGOUT)=f(IRG)/7*64*4/2=4.4434MHz (10% off reqd' 4.9152MHz)
	  ELSE
        MOV	  	#%00010000,ICGC2	; N=6,R=2, f(ICGOUT)=f(IRG)/7*64*6/1=13.330MHz (10% off reqd' 14.7456MHz)
	  ENDIF
        								          ; f(BUS)=f(ICGOUT)/2 !